Add rpmsg virtual gpio driver support.
i.MX7ULP GPIO PTA and PTB resource are managed by M4 core, setup one
simple protocol with M4 core based on RPMSG virtual IO to let A core
access such GPIOs that is what the driver do.

Reviewed-by: Richard Zhu <hongxing.zhu@nxp.com>
Reviewed-by: Robin Gong <yibin.gong@nxp.com>
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>

Add rpmsg gpio PTA and PTB support.
Since currently M4 image support dynamical channel allocation,
and reserve below memory for kernel service and app channel:
        * --0x9FF00000~0x9FF0FFFF: pmic,pm,audio,keys,gpio
        * --0x9FF10000~0x9FF1FFFF: pingpong,virtual tty

Change the rpmsg instances of  A core part to sync with M core.

Test M4 image built from Wayne Feng, M4 image commit ID: b1321d4aca82

Reviewed-by: Richard Zhu <hongxing.zhu@nxp.com>
Reviewed-by: Robin Gong <yibin.gong@nxp.com>
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>

Enable CONFIG_GPIO_IMX_RPMSG to support rpmsg gpio driver in default.

Reviewed-by: Richard Zhu <hongxing.zhu@nxp.com>
Reviewed-by: Robin Gong <yibin.gong@nxp.com>
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>

USB2 PLL use ring VCO, when the PLL power up, the ring VCO’s supply also
ramp up. There is a possibility that the ring VCO start oscillation at
multi nodes in this phase, especially for VCO which has many stages, then
the multiwave will kept until PLL power down. Hold_ring_off(bit11) can
force the VCO in one determined state when VCO supply start ramp up, to
avoid this multiwave issue. Per IC design's suggestion it's better this
bit can be off from 25us after pll power up to 25us before USB TX/RX.

Acked-by: Peter Chen <peter.chen@nxp.com>
Signed-off-by: Li Jun <jun.li@nxp.com>
(cherry picked from commit a094377f04c9ed2c8e702ee7bfab843caa03eb96)

On our i.MX6 SOC, the DIGPROG register is used for represent the
SOC ID and silicon revision. The revision has two part: MAJOR and
MINOR. each is represented in 8 bits in the register.

  bits [15:8]: reflect the MAJOR part of the revision;
  bits [7:0]: reflect the MINOR part of the revision;

In our linux kernel, the soc revision is represented in 8 bits. MAJOR
part and MINOR each occupy 4 bits.

previous method does NOT take care about the MAJOR part in DIGPROG register.
So reformat the revision read from the HW to compatible the revision format
used in kernel.

Signed-off-by: Bai Ping <ping.bai@nxp.com>
(cherry picked from commit cf6fa14)

Previous code don't take care about the i.MX6QP revision update of
new TO. So improve the code to include future TO support for i.MX6QP.

Signed-off-by: Bai Ping <ping.bai@nxp.com>
(cherry picked from commit 513e1c9)