diff --git a/soft-ip-driver-user-guides/miv-rv32-hal/miv-rv32-hal-user-guide.md b/soft-ip-driver-user-guides/miv-rv32-hal/miv-rv32-hal-user-guide.md
index a7e85a4..c027dd0 100644
--- a/soft-ip-driver-user-guides/miv-rv32-hal/miv-rv32-hal-user-guide.md
+++ b/soft-ip-driver-user-guides/miv-rv32-hal/miv-rv32-hal-user-guide.md
@@ -30,6 +30,7 @@
- [MIV_RV32_EXT_TIMECMP](#mivrv32exttimecmp)
- [External IRQ](#external-irq)
- [RISC-V Specification Interrupts](#risc-v-specification-interrupts)
+ - [BootROM](#bootrom)
- [SUBSYS Register Configuration](#subsys-register-configuration)
- [SUBSYS Interrupt Request Masks](#subsys-interrupt-request-masks)
@@ -48,6 +49,7 @@
- [MRV_clear_soft_irq](#mrvclearsoftirq)
- [SysTick_Handler](#systickhandler)
- [MRV_systick_config](#mrvsystickconfig)
+ - [MRV_BootROM_reconfigure](#mrvbootromreconfigure)
- [MRV32_subsys_enable_irq](#mrv32subsysenableirq)
- [MRV32_subsys_disable_irq](#mrv32subsysdisableirq)
- [MRV32_subsys_clear_irq](#mrv32subsysclearirq)
@@ -91,11 +93,11 @@ your designs to MIV_RV32 v3.1 (and subsequent IP releases) for the latest
enhancements, bug fixes, and support.
## MIV_RV32 V3.1
-This is the latest release of the MIV_RV32 Soft IP core. For more details, refer
-to the MIV_RV32 User Guide
-The MIV_RV32 Core as well as this document use the terms defined below:
+The MIV_RV32 Core and this document use the following terms:
- SUBSYS - Processor Subsystem for RISC-V
- OPSRV - Offload Processor Subsystem for RISC-V
@@ -108,13 +110,13 @@ The MIV_RV32 Core as well as this document use the terms defined below:
- ISR - Interrupt Service Routine
# Customizing MIV_RV32 HAL
-To use the HAL with older releases of MIV_RV32, preprocessor macros have been
+To use the HAL with older releases of MIV_RV32 preprocessor, macros have been
provided. Using these macros, any of the IP version is targeted. The HAL is used
-to target any of the mentioned platforms by adding the following macros in the
-way : Project Properties > C/C++ Build > Settings > Preprocessor in Assembler
-and Compiler settings. The table below shows the macros corresponding to the MIV
-Core being used in your libero project. By default, the HAL targets v3.1 of the
-IP core and no macros need to be set for this configutation.
+to target the mentioned platforms by adding the following macros in Project
+Properties > C/C++ Build > Settings > Preprocessor available in the Assembler
+and Compiler settings. The following table shows the macros corresponding to the
+MIV Core being used in your libero project. By default, the HAL targets v3.1 of
+the IP core and no macros need to be set for this configutation.
| Libero MI-V Soft IP Version | SoftConsole Macro |
| -----|-----|
@@ -157,7 +159,7 @@ For changes in MIE register map, see the [MIE Register Map for MIV_RV32 v3.0](#m
SUBSYSR is currently not being used by the core and is Reserved for future use.
The mtvec.BASE field corresponds to the bits [31:2], where mtvec stands for
-Machine Trap Vector, and all traps set the PC to the the value stored in the
+Machine Trap Vector, and all traps set the PC to the value stored in the
mtvec.BASE field when in Non-Vectored mode. In this case, a generic trap handler
is as an interrupt service routine.
@@ -190,7 +192,7 @@ When an interrupt is taken and Floating Point instructions are used in the ISR,
the floating point register context must be saved to resume the application
correctly. To use this feature, enable the provided macro in the Softconsole
build settings. This feature is turned off by default as it adds overhead which
-is not required when the ISR does not used FP insturctions and saving the
+is not required when the ISR does not use FP insturctions and saving the
general purpose register context is sufficient.
| Macro Name | Definition |
@@ -198,12 +200,11 @@ general purpose register context is sufficient.
| MIV_FP_CONTEXT_SAVE | Define to save the FP register file |
## SUBSYS - SubSystem for RISC-V
-SUBSYS stands for SubSystem for RISC-V. This was previously (MIV_RV32 v3.0)
-known as OPSRV, which stands for "Offload Processor Subsystem
-for RISC-V". See
-the earlier versions of the handbook for more details. In the latest release of
-the MIV_RV32 IP core v3.1, OPSRV has been renamed to SUBSYS. The MIV_RV32 HAL
-now uses SUBSYS instead of OPSRV.
+SUBSYS stands for SubSystem for RISC-V. Refer to the MIV_RV32 v3.1 Handbook for
+more details.
+NOTE: This was previously (MIV_RV32 v3.0) known as OPSRV, which stands for
+"Offload Processor Subsystem for RISC-V". See the earlier versions of the
+handbook for more details. The MIV_RV32 HAL now uses SUBSYS instead of OPSRV.
@@ -311,8 +312,8 @@ interrupts, the names of the additional interrupts correspond to the names as
used in the MIV_RV32 handbook. Please refer the MIV_RV32 handbook for more
details.
-All the interrups, provided by the MIV_RV32 core, follow the interrupt priority
-order and register description as mentioned in the RISC-V spec.
+All the interrups, provided by the MIV_RV32 core, following table shows the
+interrupt priority order and register description as mentioned in the RISC-V spec.
| Macro Name | Value | Description |
| -----|-----|-----|
@@ -322,12 +323,45 @@ order and register description as mentioned in the RISC-V spec.
+
+
+
+## BootROM
+When BootROM is enabled, on reset, the core copies data from a memory mapped
+source memory into a destination memory location and then the core boots from
+the destination memory location. The source start or end addresses and the
+destination start address can be provided through GUI inputs. If the
+Reconfigurable option is enabled, then the addresses become software
+reconfigurable, which can be used with a soft reset to reboot and run alternative
+code.The source and destination memory must be a memory mapped location
+accessible by the core across the full transfer size.
+
+MTVEC address - By default, the mtvec.BASE is set at Reset Vector Address + 0x04.
+When the BootROM is enabled, the mtvec.BASE is set at destination address + 0x04.
+When using Reconfigurable BootROM, the MTVEC register needs to be defined
+and programmed through software.
+
+Reset Behaviour - With the BootROM feature enabled, upon reset, the PC takes on
+the value of the BootROM dest_addr. When the BootROM is enabled, ensure that the
+boot code linker script matches the dest_addr, since booting starts from the
+destination_addr.
+
+BootROM Register Map:
+
+| Name | Address | Description |
+| -----|-----|-----|
+| src_start_addr | 0xA100 | Core copies data beginning here |
+| src_end_addr | 0xA104 | Last address copied by BootROM |
+| destination_addr | 0xA108 | Destination memory beginning from here |
+
+
## SUBSYS Register Configuration
For the SUBSYS registers configutation, the following definitions are used in
-the SUBSUS API functions. For example, to raise soft interrupts, enable parity
+the SUBSYS API functions. For example, to raise soft interrupts, enable parity
checks, soft reset, and so on.
| Configuration | Value | Description |
@@ -348,11 +382,11 @@ and interrupt pending register.
| Interrupt Mask | Value | Description |
| -----|-----|-----|
-| SUBSYS_TCM_ECC_CE_IRQ | 0x01u | TCM ECC controllable error irq enable |
-| SUBSYS_TCM_ECC_UCE_IRQ | 0x02u | TCM ECC uncontrollable error irq enable |
-| SUBSYS_AXI_WR_RESP_IRQ | 0x10u | AXI write response error irq enable |
-| SUBSYS_ICACHE_ECC_CE_IRQ | 0x40u | Icache ECC Correctable error irq |
-| SUBSYS_ICACHE_ECC_UCE_IRQ | 0x80u | Icache ECC Uncorrectable error irq |
+| SUBSYS_TCM_ECC_CE_IRQ | 0x01u | TCM ECC controllable error IRQ enable |
+| SUBSYS_TCM_ECC_UCE_IRQ | 0x02u | TCM ECC uncontrollable error IRQ enable |
+| SUBSYS_AXI_WR_RESP_IRQ | 0x10u | AXI write response error IRQ enable |
+| SUBSYS_ICACHE_ECC_CE_IRQ | 0x40u | Icache ECC Correctable error IRQ |
+| SUBSYS_ICACHE_ECC_UCE_IRQ | 0x80u | Icache ECC Uncorrectable error IRQ |
| SUBSYS_BASE_ADDR | 0x6000u | Base address of the SUBSYS |
@@ -735,7 +769,7 @@ This functions returns the CORE_GPR_DED_RESET_REG bit value.
-The MRV_read_mtvec_base() function reads the mtvec base value, which is the addr
+The MRV_read_mtvec_base() function reads the mtvec base value, which is the address
used when an interrupt/trap occurs. In the mtvec register, [31:2] is the BASE
address. NOTE: The BASE address must be aligned on a 4B boundary.
@@ -1068,6 +1102,74 @@ interrupt to be triggered.
Returns 0 if successful. Returns 1 if the interrupt interval is not achieved.
+
+
+
+ --------------------------------
+
+## MRV_BootROM_reconfigure
+
+### Prototype
+
+
+
+ void
+ MRV_BootROM_reconfigure
+ (
+ uint32_t start_addr,
+ uint32_t end_addr,
+ uint32_t destination_addr
+ );
+
+
+
+
+
+### Description
+
+
+
+BootROM Address Reconfiguration
+
+Configures the BootROM registers with the source start, end, and destination
+addresses for the core when BootROM addresses are reconfigurable.
+
+
+
+
+ ---------------------------
+
+
+### Parameters
+#### start_addr
+
+
+Starting address for the BootROM copy.
+
+
+
+
+#### end_addr
+
+
+End address for the BootROM copy.
+
+
+
+
+#### destination_addr
+
+
+On Reset, the core will start running code from this memory address.
+
+
+
+
+
+### Return
+
+
+