From d623bc833e796480b243666064bbdee46bd2f027 Mon Sep 17 00:00:00 2001
From: Nic30 <nic30@seznam.cz>
Date: Thu, 6 Jun 2024 22:40:44 +0200
Subject: [PATCH] test: update basic_hdl_sim_model test files to new hwt names

---
 tests/basic_hdl_sim_model/expected/simple_subunit.py.txt | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/tests/basic_hdl_sim_model/expected/simple_subunit.py.txt b/tests/basic_hdl_sim_model/expected/simple_subunit.py.txt
index 726c604e..a82c9245 100644
--- a/tests/basic_hdl_sim_model/expected/simple_subunit.py.txt
+++ b/tests/basic_hdl_sim_model/expected/simple_subunit.py.txt
@@ -20,7 +20,7 @@ class submodule0(BasicRtlSimModel):
         # internal signals
         # component instances
     def _init_body(self):
-        self._interfaces = (
+        self._hwIOs = (
             self.io.a,
             self.io.b,
         )
@@ -61,7 +61,7 @@ class SimpleSubunit(BasicRtlSimModel):
     def _init_body(self):
         connectSimPort(self, self.submodule0_inst, "sig_submodule0_a", "a")
         connectSimPort(self, self.submodule0_inst, "sig_submodule0_b", "b")
-        self._interfaces = (
+        self._hwIOs = (
             self.io.a,
             self.io.b,
             self.io.sig_submodule0_a,