start moving properties for the ports to the ports.tcl

This might allow us to set the properties for pins that are optimized away, as opposed to using the constraints that will create a whole bunch of warnings when trying to constrain a pin that isn't used in the project Also try and update the README a little more
OpenMRI · Sep 16, 2024 · c5dfb1c · c5dfb1c
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diff --git a/HDL/README.md b/HDL/README.md
@@ -37,13 +37,17 @@ Similarily, you can build the ocra_mri project for the stemlab_125_14 by calling
 ```
 make NAME=ocra_mri BOARD=stemlab_125_14
 ```
+This will build bitfiles that can be used with on a Linux installation on your Zynq so long it supports the fpga_manager. 
 
-This will build bitfiles that can be used with on a Linux installation on your Zynq so long it supports the fpga_manager. If you want to build a device tree and the associated files to create your own bootloader etc. you need to run
+Sometimes you might want to only quickly generate the project file for Vivado, which you make by calling:
+```
+make xpr NAME=ocra_mri BOARD=stemlab_125_14
+```
 
+If you want to build a device tree and the associated files to create your own bootloader etc. you need to run:
 ```
 make dtbo NAME=ocra_mri BOARD=stemlab_125_14
 ```
-
 Note that this requires the HSI tool xsct and the device tree compiler dtc.
 
 This is pretty easy, isn't it?
diff --git a/HDL/boards/stemlab_125_14/ports.tcl b/HDL/boards/stemlab_125_14/ports.tcl
@@ -26,18 +26,56 @@ create_bd_port -dir O dac_wrt_o
 create_bd_port -dir O -from 3 -to 0 dac_pwm_o
 
 ### XADC
-
-create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vp_Vn
-create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vaux0
-create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vaux1
-create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vaux9
-create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vaux8
+# create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vp_Vn
+# create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vaux0
+# create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vaux1
+# create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vaux9
+# create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vaux8
 
 ### Expansion connector
 
 create_bd_port -dir IO -from 7 -to 0 exp_p_tri_io
 create_bd_port -dir IO -from 7 -to 0 exp_n_tri_io
 
+set_property IOSTANDARD LVCMOS33 [get_ports {exp_p_tri_io[*]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {exp_n_tri_io[*]}]
+set_property SLEW FAST [get_ports {exp_p_tri_io[*]}]
+set_property SLEW FAST [get_ports {exp_n_tri_io[*]}]
+set_property DRIVE 8 [get_ports {exp_p_tri_io[*]}]
+set_property DRIVE 8 [get_ports {exp_n_tri_io[*]}]
+set_property PULLTYPE PULLUP [get_ports {exp_p_tri_io[*]}]
+set_property PULLTYPE PULLUP [get_ports {exp_n_tri_io[*]}]
+
+set_property PACKAGE_PIN G17 [get_ports {exp_p_tri_io[0]}]
+set_property PACKAGE_PIN G18 [get_ports {exp_n_tri_io[0]}]
+set_property PACKAGE_PIN H16 [get_ports {exp_p_tri_io[1]}]
+set_property PACKAGE_PIN H17 [get_ports {exp_n_tri_io[1]}]
+set_property PACKAGE_PIN J18 [get_ports {exp_p_tri_io[2]}]
+set_property PACKAGE_PIN H18 [get_ports {exp_n_tri_io[2]}]
+set_property PACKAGE_PIN K17 [get_ports {exp_p_tri_io[3]}]
+set_property PACKAGE_PIN K18 [get_ports {exp_n_tri_io[3]}]
+set_property PACKAGE_PIN L14 [get_ports {exp_p_tri_io[4]}]
+set_property PACKAGE_PIN L15 [get_ports {exp_n_tri_io[4]}]
+set_property PACKAGE_PIN L16 [get_ports {exp_p_tri_io[5]}]
+set_property PACKAGE_PIN L17 [get_ports {exp_n_tri_io[5]}]
+set_property PACKAGE_PIN K16 [get_ports {exp_p_tri_io[6]}]
+set_property PACKAGE_PIN J16 [get_ports {exp_n_tri_io[6]}]
+set_property PACKAGE_PIN M14 [get_ports {exp_p_tri_io[7]}]
+set_property PACKAGE_PIN M15 [get_ports {exp_n_tri_io[7]}]
+
 ### LED
 
 create_bd_port -dir O -from 7 -to 0 led_o
+
+set_property IOSTANDARD LVCMOS33 [get_ports {led_o[*]}]
+set_property SLEW SLOW [get_ports {led_o[*]}]
+set_property DRIVE 8 [get_ports {led_o[*]}]
+
+set_property PACKAGE_PIN F16 [get_ports {led_o[0]}]
+set_property PACKAGE_PIN F17 [get_ports {led_o[1]}]
+set_property PACKAGE_PIN G15 [get_ports {led_o[2]}]
+set_property PACKAGE_PIN H15 [get_ports {led_o[3]}]
+set_property PACKAGE_PIN K14 [get_ports {led_o[4]}]
+set_property PACKAGE_PIN G14 [get_ports {led_o[5]}]
+set_property PACKAGE_PIN J15 [get_ports {led_o[6]}]
+set_property PACKAGE_PIN J14 [get_ports {led_o[7]}]
diff --git a/HDL/boards/stemlab_125_14/ports.xdc b/HDL/boards/stemlab_125_14/ports.xdc
@@ -1,4 +1,3 @@
-
 # set_property CFGBVS VCCO [current_design]
 # set_property CONFIG_VOLTAGE 3.3 [current_design]
 
@@ -120,90 +119,76 @@ set_property PACKAGE_PIN U13 [get_ports {dac_pwm_o[3]}]
 
 ### XADC
 
-set_property IOSTANDARD LVCMOS33 [get_ports Vp_Vn_v_p]
-set_property IOSTANDARD LVCMOS33 [get_ports Vp_Vn_v_n]
-set_property IOSTANDARD LVCMOS33 [get_ports Vaux0_v_p]
-set_property IOSTANDARD LVCMOS33 [get_ports Vaux0_v_n]
-set_property IOSTANDARD LVCMOS33 [get_ports Vaux1_v_p]
-set_property IOSTANDARD LVCMOS33 [get_ports Vaux1_v_n]
-set_property IOSTANDARD LVCMOS33 [get_ports Vaux8_v_p]
-set_property IOSTANDARD LVCMOS33 [get_ports Vaux8_v_n]
-set_property IOSTANDARD LVCMOS33 [get_ports Vaux9_v_p]
-set_property IOSTANDARD LVCMOS33 [get_ports Vaux9_v_n]
-
-set_property PACKAGE_PIN K9  [get_ports Vp_Vn_v_p]
-set_property PACKAGE_PIN L10 [get_ports Vp_Vn_v_n]
-set_property PACKAGE_PIN C20 [get_ports Vaux0_v_p]
-set_property PACKAGE_PIN B20 [get_ports Vaux0_v_n]
-set_property PACKAGE_PIN E17 [get_ports Vaux1_v_p]
-set_property PACKAGE_PIN D18 [get_ports Vaux1_v_n]
-set_property PACKAGE_PIN B19 [get_ports Vaux8_v_p]
-set_property PACKAGE_PIN A20 [get_ports Vaux8_v_n]
-set_property PACKAGE_PIN E18 [get_ports Vaux9_v_p]
-set_property PACKAGE_PIN E19 [get_ports Vaux9_v_n]
+# set_property IOSTANDARD LVCMOS33 [get_ports Vp_Vn_v_p]
+# set_property IOSTANDARD LVCMOS33 [get_ports Vp_Vn_v_n]
+# set_property IOSTANDARD LVCMOS33 [get_ports Vaux0_v_p]
+# set_property IOSTANDARD LVCMOS33 [get_ports Vaux0_v_n]
+# set_property IOSTANDARD LVCMOS33 [get_ports Vaux1_v_p]
+# set_property IOSTANDARD LVCMOS33 [get_ports Vaux1_v_n]
+# set_property IOSTANDARD LVCMOS33 [get_ports Vaux8_v_p]
+# set_property IOSTANDARD LVCMOS33 [get_ports Vaux8_v_n]
+# set_property IOSTANDARD LVCMOS33 [get_ports Vaux9_v_p]
+# set_property IOSTANDARD LVCMOS33 [get_ports Vaux9_v_n]
+
+# set_property PACKAGE_PIN K9  [get_ports Vp_Vn_v_p]
+# set_property PACKAGE_PIN L10 [get_ports Vp_Vn_v_n]
+# set_property PACKAGE_PIN C20 [get_ports Vaux0_v_p]
+# set_property PACKAGE_PIN B20 [get_ports Vaux0_v_n]
+# set_property PACKAGE_PIN E17 [get_ports Vaux1_v_p]
+# set_property PACKAGE_PIN D18 [get_ports Vaux1_v_n]
+# set_property PACKAGE_PIN B19 [get_ports Vaux8_v_p]
+# set_property PACKAGE_PIN A20 [get_ports Vaux8_v_n]
+# set_property PACKAGE_PIN E18 [get_ports Vaux9_v_p]
+# set_property PACKAGE_PIN E19 [get_ports Vaux9_v_n]
 
 ### Expansion connector
 
-set_property IOSTANDARD LVCMOS33 [get_ports {exp_p_tri_io[*]}]
-set_property IOSTANDARD LVCMOS33 [get_ports {exp_n_tri_io[*]}]
-set_property SLEW FAST [get_ports {exp_p_tri_io[*]}]
-set_property SLEW FAST [get_ports {exp_n_tri_io[*]}]
-set_property DRIVE 8 [get_ports {exp_p_tri_io[*]}]
-set_property DRIVE 8 [get_ports {exp_n_tri_io[*]}]
-set_property PULLTYPE PULLUP [get_ports {exp_p_tri_io[*]}]
-set_property PULLTYPE PULLUP [get_ports {exp_n_tri_io[*]}]
-
-set_property PACKAGE_PIN G17 [get_ports {exp_p_tri_io[0]}]
-set_property PACKAGE_PIN G18 [get_ports {exp_n_tri_io[0]}]
-set_property PACKAGE_PIN H16 [get_ports {exp_p_tri_io[1]}]
-set_property PACKAGE_PIN H17 [get_ports {exp_n_tri_io[1]}]
-set_property PACKAGE_PIN J18 [get_ports {exp_p_tri_io[2]}]
-set_property PACKAGE_PIN H18 [get_ports {exp_n_tri_io[2]}]
-set_property PACKAGE_PIN K17 [get_ports {exp_p_tri_io[3]}]
-set_property PACKAGE_PIN K18 [get_ports {exp_n_tri_io[3]}]
-set_property PACKAGE_PIN L14 [get_ports {exp_p_tri_io[4]}]
-set_property PACKAGE_PIN L15 [get_ports {exp_n_tri_io[4]}]
-set_property PACKAGE_PIN L16 [get_ports {exp_p_tri_io[5]}]
-set_property PACKAGE_PIN L17 [get_ports {exp_n_tri_io[5]}]
-set_property PACKAGE_PIN K16 [get_ports {exp_p_tri_io[6]}]
-set_property PACKAGE_PIN J16 [get_ports {exp_n_tri_io[6]}]
-set_property PACKAGE_PIN M14 [get_ports {exp_p_tri_io[7]}]
-set_property PACKAGE_PIN M15 [get_ports {exp_n_tri_io[7]}]
-
-set_property IOSTANDARD LVCMOS33 [get_ports exp_p_trg]
-set_property SLEW FAST [get_ports exp_p_trg]
-set_property DRIVE 8 [get_ports exp_p_trg]
-
-set_property PACKAGE_PIN M14 [get_ports exp_p_trg]
-
-set_property IOSTANDARD LVCMOS33 [get_ports {exp_n_alex[*]}]
-set_property SLEW FAST [get_ports {exp_n_alex[*]}]
-set_property DRIVE 8 [get_ports {exp_n_alex[*]}]
-
-set_property PACKAGE_PIN L15 [get_ports {exp_n_alex[0]}]
-set_property PACKAGE_PIN L17 [get_ports {exp_n_alex[1]}]
-set_property PACKAGE_PIN J16 [get_ports {exp_n_alex[2]}]
-set_property PACKAGE_PIN M15 [get_ports {exp_n_alex[3]}]
+# set_property IOSTANDARD LVCMOS33 [get_ports {exp_p_tri_io[*]}]
+# set_property IOSTANDARD LVCMOS33 [get_ports {exp_n_tri_io[*]}]
+# set_property SLEW FAST [get_ports {exp_p_tri_io[*]}]
+# set_property SLEW FAST [get_ports {exp_n_tri_io[*]}]
+# set_property DRIVE 8 [get_ports {exp_p_tri_io[*]}]
+# set_property DRIVE 8 [get_ports {exp_n_tri_io[*]}]
+# set_property PULLTYPE PULLUP [get_ports {exp_p_tri_io[*]}]
+# set_property PULLTYPE PULLUP [get_ports {exp_n_tri_io[*]}]
+
+# set_property PACKAGE_PIN G17 [get_ports {exp_p_tri_io[0]}]
+# set_property PACKAGE_PIN G18 [get_ports {exp_n_tri_io[0]}]
+# set_property PACKAGE_PIN H16 [get_ports {exp_p_tri_io[1]}]
+# set_property PACKAGE_PIN H17 [get_ports {exp_n_tri_io[1]}]
+# set_property PACKAGE_PIN J18 [get_ports {exp_p_tri_io[2]}]
+# set_property PACKAGE_PIN H18 [get_ports {exp_n_tri_io[2]}]
+# set_property PACKAGE_PIN K17 [get_ports {exp_p_tri_io[3]}]
+# set_property PACKAGE_PIN K18 [get_ports {exp_n_tri_io[3]}]
+# set_property PACKAGE_PIN L14 [get_ports {exp_p_tri_io[4]}]
+# set_property PACKAGE_PIN L15 [get_ports {exp_n_tri_io[4]}]
+# set_property PACKAGE_PIN L16 [get_ports {exp_p_tri_io[5]}]
+# set_property PACKAGE_PIN L17 [get_ports {exp_n_tri_io[5]}]
+# set_property PACKAGE_PIN K16 [get_ports {exp_p_tri_io[6]}]
+# set_property PACKAGE_PIN J16 [get_ports {exp_n_tri_io[6]}]
+# set_property PACKAGE_PIN M14 [get_ports {exp_p_tri_io[7]}]
+# set_property PACKAGE_PIN M15 [get_ports {exp_n_tri_io[7]}]
+
 
 ### SATA connector
 
-set_property IOSTANDARD DIFF_HSTL_I_18 [get_ports daisy_p_o[*]]
-set_property IOSTANDARD DIFF_HSTL_I_18 [get_ports daisy_n_o[*]]
+# set_property IOSTANDARD DIFF_HSTL_I_18 [get_ports daisy_p_o[*]]
+# set_property IOSTANDARD DIFF_HSTL_I_18 [get_ports daisy_n_o[*]]
 
-set_property IOSTANDARD DIFF_HSTL_I_18 [get_ports daisy_p_i[*]]
-set_property IOSTANDARD DIFF_HSTL_I_18 [get_ports daisy_n_i[*]]
+# set_property IOSTANDARD DIFF_HSTL_I_18 [get_ports daisy_p_i[*]]
+# set_property IOSTANDARD DIFF_HSTL_I_18 [get_ports daisy_n_i[*]]
 
-set_property PACKAGE_PIN T12 [get_ports {daisy_p_o[0]}]
-set_property PACKAGE_PIN U12 [get_ports {daisy_n_o[0]}]
+# set_property PACKAGE_PIN T12 [get_ports {daisy_p_o[0]}]
+# set_property PACKAGE_PIN U12 [get_ports {daisy_n_o[0]}]
 
-set_property PACKAGE_PIN U14 [get_ports {daisy_p_o[1]}]
-set_property PACKAGE_PIN U15 [get_ports {daisy_n_o[1]}]
+# set_property PACKAGE_PIN U14 [get_ports {daisy_p_o[1]}]
+# set_property PACKAGE_PIN U15 [get_ports {daisy_n_o[1]}]
 
-set_property PACKAGE_PIN P14 [get_ports {daisy_p_i[0]}]
-set_property PACKAGE_PIN R14 [get_ports {daisy_n_i[0]}]
+# set_property PACKAGE_PIN P14 [get_ports {daisy_p_i[0]}]
+# set_property PACKAGE_PIN R14 [get_ports {daisy_n_i[0]}]
 
-set_property PACKAGE_PIN N18 [get_ports {daisy_p_i[1]}]
-set_property PACKAGE_PIN P19 [get_ports {daisy_n_i[1]}]
+# set_property PACKAGE_PIN N18 [get_ports {daisy_p_i[1]}]
+# set_property PACKAGE_PIN P19 [get_ports {daisy_n_i[1]}]
 
 ### LED
 

diff --git a/HDL/projects/ocra_mri/block_design.tcl b/HDL/projects/ocra_mri/block_design.tcl
@@ -415,16 +415,6 @@ set_property -dict [list CONFIG.Register_PortB_Output_of_Memory_Primitives {true
 #
 # try to connect the bottom 8 bits of the pulse output of the sequencer to the positive gpoi
 #
-# Delete input/output port
-delete_bd_objs [get_bd_ports exp_p_tri_io]
-delete_bd_objs [get_bd_ports exp_n_tri_io]
-
-# Create newoutput port
-create_bd_port -dir O -from 7 -to 0 exp_p_tri_io
-#connect_bd_net [get_bd_pins exp_p_tri_io] [get_bd_pins trigger_slice_0/Dout]
-
-# Create output port for the SPI stuff
-create_bd_port -dir O -from 7 -to 0 exp_n_tri_io
 
 # 09/2019: For the new board we are doing this differently. The SPI bus will use seven pins on the n side of the header
 #          and the txgate will use the eight' pin on the n side