fix(csr): check inst exception for Zicbom & Zicboz #537
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@Tang-Haojin May this PR should be merged into master before release? |
sinceforYy
reviewed
Sep 27, 2024
src/isa/riscv64/instr/rvcbo/exec.h
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| @@ -23,6 +23,13 @@ | |||
| #define CACHE_BLOCK_OPS (CACHE_BLOCK_SIZE / CACHE_OP_SPLIT_SIZE) | |||
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| def_EHelper(cbo_zero) { | |||
| // check illegal instruction exception | |||
| if(!cpu.v && ((cpu.mode != MODE_M && !menvcfg->cbze) || (cpu.mode == MODE_U && !senvcfg->cbze))){ | |||
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The CBO Spec only says it is not in M mode, maybe it is in HS/HU/VS/VU mode.
sinceforYy
approved these changes
Sep 29, 2024
src/isa/riscv64/instr/rvcbo/exec.h
Outdated
| @@ -23,6 +23,13 @@ | |||
| #define CACHE_BLOCK_OPS (CACHE_BLOCK_SIZE / CACHE_OP_SPLIT_SIZE) | |||
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| def_EHelper(cbo_zero) { | |||
| // check illegal instruction exception | |||
| if((cpu.mode != MODE_M && !menvcfg->cbze) || (cpu.mode == MODE_U && !senvcfg->cbze)){ | |||
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In addition, ModeU should be ModeHU. if ((cpu.mode != MODE_M && !menvcfg->cbze) || (!cpu.v && cpu.mode == MODE_U && !senvcfg->cbze)) {
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