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fix(csr): check inst exception for Zicbom & Zicboz #537

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fix(csr): check inst exception for Zicbom & Zicboz #537

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dd3b05f
fix(csr): check inst exception for Zicbom & Zicboz
Sep 13, 2024
0be1bf5
fix(csr): fix illegal inst exception condition for Zicbom & Zicboz
Sep 27, 2024
8514c6a
fix(csr): fix illegal inst exception condition for Zicbom & Zicboz
Sep 29, 2024
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32 changes: 32 additions & 0 deletions src/isa/riscv64/instr/rvcbo/exec.h
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Original file line number Diff line number Diff line change
Expand Up @@ -23,6 +23,13 @@
#define CACHE_BLOCK_OPS (CACHE_BLOCK_SIZE / CACHE_OP_SPLIT_SIZE)

def_EHelper(cbo_zero) {
// check illegal instruction exception
if(!cpu.v && ((cpu.mode != MODE_M && !menvcfg->cbze) || (cpu.mode == MODE_U && !senvcfg->cbze))){
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cbo-cbze

The CBO Spec only says it is not in M ​​mode, maybe it is in HS/HU/VS/VU mode.

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Make sense, already fix it.

longjmp_exception(EX_II);
} else if(cpu.v && ((cpu.mode == MODE_S && !henvcfg->cbze) || (cpu.mode == MODE_U && !(henvcfg->cbze && senvcfg->cbze)))){
longjmp_exception(EX_VI);
}

rtlreg_t* addr_p = dsrc1;
rtlreg_t block_addr = *addr_p & ~CACHE_BLOCK_MASK;
for (int i = 0; i < CACHE_BLOCK_OPS; i++) {
Expand All @@ -33,6 +40,13 @@ def_EHelper(cbo_zero) {
}

def_EHelper(cbo_zero_mmu) {
// check illegal instruction exception
if(!cpu.v && ((cpu.mode != MODE_M && !menvcfg->cbze) || (cpu.mode == MODE_U && !senvcfg->cbze))){
longjmp_exception(EX_II);
} else if(cpu.v && ((cpu.mode == MODE_S && !henvcfg->cbze) || (cpu.mode == MODE_U && !(henvcfg->cbze && senvcfg->cbze)))){
longjmp_exception(EX_VI);
}

rtlreg_t* addr_p = dsrc1;
rtlreg_t block_addr = *addr_p & ~CACHE_BLOCK_MASK;
for (int i = 0; i < CACHE_BLOCK_OPS; i++) {
Expand All @@ -43,16 +57,34 @@ def_EHelper(cbo_zero_mmu) {
}

def_EHelper(cbo_inval) {
// check illegal instruction exception
if(!cpu.v && ((cpu.mode != MODE_M && menvcfg->cbie == 0) || (cpu.mode == MODE_U && senvcfg->cbie == 0))){
longjmp_exception(EX_II);
} else if(cpu.v && ((cpu.mode == MODE_S && henvcfg->cbie == 0) || (cpu.mode == MODE_U && (henvcfg->cbie == 0 || senvcfg->cbie == 0)))){
longjmp_exception(EX_VI);
}
// do nothing
IFNDEF(CONFIG_DIFFTEST_REF_NEMU, difftest_skip_dut(1, 2));
}

def_EHelper(cbo_flush) {
// check illegal instruction exception
if(!cpu.v && ((cpu.mode != MODE_M && !menvcfg->cbcfe) || (cpu.mode == MODE_U && !senvcfg->cbcfe))){
longjmp_exception(EX_II);
} else if(cpu.v && ((cpu.mode == MODE_S && !henvcfg->cbcfe) || (cpu.mode == MODE_U && !(henvcfg->cbcfe && senvcfg->cbcfe)))){
longjmp_exception(EX_VI);
}
// do nothing
IFNDEF(CONFIG_DIFFTEST_REF_NEMU, difftest_skip_dut(1, 2));
}

def_EHelper(cbo_clean) {
// check illegal instruction exception
if(!cpu.v && ((cpu.mode != MODE_M && !menvcfg->cbcfe) || (cpu.mode == MODE_U && !senvcfg->cbcfe))){
longjmp_exception(EX_II);
} else if(cpu.v && ((cpu.mode == MODE_S && !henvcfg->cbcfe) || (cpu.mode == MODE_U && !(henvcfg->cbcfe && senvcfg->cbcfe)))){
longjmp_exception(EX_VI);
}
// do nothing
IFNDEF(CONFIG_DIFFTEST_REF_NEMU, difftest_skip_dut(1, 2));
}
13 changes: 13 additions & 0 deletions src/isa/riscv64/local-include/csr.h
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Original file line number Diff line number Diff line change
Expand Up @@ -921,6 +921,19 @@ CSR_STRUCT_START(stval)
CSR_STRUCT_END(stval)

CSR_STRUCT_START(senvcfg)
uint64_t fiom : 1; // [0]
uint64_t pad0 : 3; // [3:1]
uint64_t cbie : 2; // [5:4]
uint64_t cbcfe : 1; // [6]
uint64_t cbze : 1; // [7]
uint64_t pad1 : 24;// [31:8]
uint64_t pmm : 2; // [33:32]
uint64_t pad3 : 25;// [58:34]
uint64_t dte : 1; // [59]
uint64_t cde : 1; // [60]
uint64_t adue : 1; // [61]
uint64_t pbmte : 1; // [62]
uint64_t stce : 1; // [63]
CSR_STRUCT_END(senvcfg)

CSR_STRUCT_START(satp)
Expand Down