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OpenXiangShan / riscv-isa-sim Public

forked from riscv-software-src/riscv-isa-sim

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CI for difftest

config(XIANGSHAN): Add Svpbmt, Zicbom & Zicboz extension and set menvcfg/henvcfg init value #37

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config(XIANGSHAN): Add Svpbmt, Zicbom & Zicboz extension and set menvcfg/henvcfg init value

config(XIANGSHAN): Add Svpbmt, Zicbom & Zicboz extension and set menvcfg/henvcfg init value #37

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Build spike-so for difftest (rocket_chip)

Build spike-so for difftest (rocket_chip)

succeeded Sep 18, 2024 in 5m 5s

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