fix(csr): htinst/mtinst are always written 0 when trap in XiangShan #33
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Currently, XiangShan only support writing 0 to htinst & mtinst CSRs when trap occurs. To align with XiangShan, this patch wraps the update of htinst & mtinst CSRs in take_trap function.
huxuan0307
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Sep 10, 2024
cebarobot
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Sep 14, 2024
This reverts commit 347cd0e (#33). According to RISC-V priv spec, htinst/mtinst could be zero when traps into HS/M-mode, except the both following conditions are met: * the fault is caused by an implicit memory access for VS-stage address translation * a nonzero value (the faulting guest physical address) is written to mtval2 or htval Actually, XiangShan would write a nonzero value in such trap, so mtinst could not be written 0. Acctually, spike only implements this nonzero situation for htinst/mtinst, so no more warps are needed.
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Currently, XiangShan only support writing 0 to htinst & mtinst CSRs when trap occurs. To align with XiangShan, this patch wraps the update of htinst & mtinst CSRs in take_trap function.