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revert(csr): htinst/mtinst should follow the origin spike behaviour #39

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merged 1 commit into from
Sep 14, 2024

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This patch reverts #33. According to RISC-V priv spec, htinst/mtinst could be zero when traps into HS/M-mode, except the both following conditions are met:

  • the fault is caused by an implicit memory access for VS-stage address translation
  • a nonzero value (the faulting guest physical address) is written to mtval2 or htval

Actually, XiangShan would write a nonzero value in such trap, so mtinst could not be written 0.

Acctually, spike only implements this nonzero situation for htinst/mtinst, so no more warps are needed.

@cebarobot cebarobot merged commit 2091e00 into difftest Sep 14, 2024
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@cebarobot cebarobot deleted the revert-33-fix-tinst branch September 14, 2024 03:41
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