diff --git a/cpu/cortexm_common/Makefile.include b/cpu/cortexm_common/Makefile.include
index 2d220a8f7938..fc181b053010 100644
--- a/cpu/cortexm_common/Makefile.include
+++ b/cpu/cortexm_common/Makefile.include
@@ -31,6 +31,11 @@ LINKFLAGS += $(if $(ROM_OFFSET),$(LINKFLAGPREFIX)--defsym=_rom_offset=$(ROM_OFFS
 # FW_ROM_LEN: rom length to use for firmware linking. Allows linking only in a section of the rom.
 LINKFLAGS += $(if $(FW_ROM_LEN),$(LINKFLAGPREFIX)--defsym=_fw_rom_length=$(FW_ROM_LEN))
 
+# Cortex-M3+ doesn't need the idle thread
+ifneq (,$(filter cortex-m2% cortex-m4% cortex-m3% cortex-m7%,$(CPU_ARCH)))
+  DISABLE_MODULE += core_idle_thread
+endif
+
 # Cortex-M0+/1/3/4/7 riotboot settings
 
 # From ARMv7-M (M4, M3, M7) architecture reference manual, section B1.5.3
diff --git a/cpu/cortexm_common/thread_arch.c b/cpu/cortexm_common/thread_arch.c
index d4d5b02478cc..e7ec8fb794f8 100644
--- a/cpu/cortexm_common/thread_arch.c
+++ b/cpu/cortexm_common/thread_arch.c
@@ -446,3 +446,24 @@ void __attribute__((used)) isr_svc(void)
     SCB->ICSR |= SCB_ICSR_PENDSVSET_Msk;
 }
 #endif /* MODULE_CORTEXM_SVC */
+
+void sched_arch_idle(void)
+{
+    /* by default, PendSV has the same priority as other ISRs.
+     * In this function, we temporarily lower the priority (set higher value),
+     * allowing other ISRs to interrupt.
+     *
+     * According to [this](http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dai0321a/BIHJICIE.html),
+     * dynamically changing the priority is not supported on CortexM0(+).
+     */
+    NVIC_SetPriority(PendSV_IRQn, CPU_CORTEXM_PENDSV_IRQ_PRIO + 1);
+    __DSB();
+    __ISB();
+#ifdef MODULE_PM_LAYERED
+    void pm_set_lowest(void);
+    pm_set_lowest();
+#else
+    __WFI();
+#endif
+    NVIC_SetPriority(PendSV_IRQn, CPU_CORTEXM_PENDSV_IRQ_PRIO);
+}