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I intended to add vssd1_ext, vssd2_ext, vccd1_ext and vccd2_ext ports to the gl verilog for caravel chip_io.v. However, after copying vccd2_pad in the port list, I forgot to change it to vccd2_ext.
netgen
1.5.276
I intended to add
vssd1_ext
,vssd2_ext
,vccd1_ext
andvccd2_ext
ports to the gl verilog for caravelchip_io.v
. However, after copyingvccd2_pad
in the port list, I forgot to change it tovccd2_ext
.There are 2
vccd2_pad
ports and novccd2_ext
port.Later in the file, I did explicitly define
netgen does not flag an undefined port error for
vccd2_ext
.I think that netgen should check the port list and the port direction declaration and flag an error if either is missing.
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