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storeFresh unused : trap-store_access_fault #111
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Hi, i think this is the combination of a few things :
Maybe the best would be to provide NaxRiscv generation with instead of That way only rv region add 0 0 0000000080000000 0000000080000000 would be considered as cached by Nax |
Once this change has been made, the test becomes infinite: it loops between "trap_store_access_fault" and "trap_store_address_misaligned"
Spike log
Separate issue: Does nax support unaligned instructions? |
As spike do agree with that behaviour, i would say that it is either OK, either that is the riscv-dv configuration/generation which need tweeks to avoid this.
No it doesn't, when running linux, opensbi emulate them in machine mode. |
In this case :
NaxRiscv/src/main/scala/naxriscv/Gen.scala Line 480 in bc18f66
|
I think that would be great, PR welcome :) |
Hi,
After running a program generated by riscv-dv for rv64imafdc, accessing address 0x7fffff20 generates an exception (trap_store_access_fault) in spike, but the DUT does the commit and RVLS detects a commit error. Here is the error message during execution
[info] commit error [info] - storeFresh unused ???
Dump
Spike log
Tracer log
Everything you need to debug or reproduce the execution is in the attached file:
debug_riscv-dv2.zip
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