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Inaccurate switch-is verilog generation #946
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Hi, If you check the switch(args), you can also specify additional stuff to relax / be more specific about the handeling of the default statement : So i think if you set coverUnreachable to true, it may be good ? |
There could be a tempRes := 0 to specify a default value, if we agree on the same policy as when clause. tempRes := 0
when(cond) {
tempRes := 1
} Then the consistent design policy maintained. |
Undocumented features <3 xD
If I get a pointer on where and how to enable/implement that I could try to create a pull request in SpinalHDL. If that is not too hard to implement, I havent done anything in the guts of SpinalHDL yet. |
I think it is important to get a broad consensus before you start coding, which is a kind of policy. It could be to search for "ASSIGNMENT OVERLAP" in the code to get a clue, then you can find the place for checking where switch takes a position. |
I don't understand 😅 is this issue is turning itself into a feature suggestion, which still requires agreement? I think I understand what the implementation of the feature would look like, but not the actual feature (what will it make it possible to do for the user?). |
IMO, if the policy is consistent than it would be easy for user to study and understand. |
I agree to that, but i guess the actual detail behind it matters obviously.
In the code I posted above this following would work (check the "HERE"): val aluArea = new Area{
val tempRes = UInt(32 bits)
// HERE: this doesnt work yet and would be of same use _as_ the default statement, but causing an ASSIGNMENT OVERLAP at the moment
// tempRes := 0 // default value to not infer latch in case of incomplete mux
switch(io.alu.operation){
is(CombOperation.add){
tempRes := io.alu.opA + io.alu.opB
}
is(CombOperation.shift){
tempRes := io.alu.opA |<< io.alu.opC
}
is(CombOperation.sub){
tempRes := (io.alu.opA - io.alu.opB)
}
is(CombOperation.xor){
tempRes := io.alu.opA ^ io.alu.opB
}
is(CombOperation.map){
tempRes := ((io.alu.opA ^ io.alu.opB) >> io.alu.opC) ^ 0x33ff11a1
}
// this can work by switch(op, coverUnreachable = true)
// default{
// tempRes := 0
// }
}
} As Readon mentioned it would be a bit more consistent with the when statement where implicitly it works (to usually prevent a latch for example)
If that is really good for case-statement aswell is not fully clear even to me, I asked out of interest as I stumbled on this when I wrote some tutorial examples for students. With |
It's a little bit complex, that I tried to remove the "ASSIGNMENT OVERLAP" check to switch. However, if the default value is not assigned, then "LATCH DETECTED" is reported. It's reasonable, if there is no default value assigned, when clause also would report this error also. So the thing is about a decision to make, if the default value for switch signal is a must then a bunch of existing code would break. If not assigning with default value would cause a report of "ASSIGNMENT OVERLAP". The proper way now is to use "coverUnreachable". |
That actually makes a lot of sense, changing the would likely break a lot of existing code. And since coverUnreachable exist it should then just be documented. |
If it's applicable, would you add this into the documentation? :) |
Heyo,
I'm currently writing some basic SpinalHDL examples and encountered some case where the SpinalHDL description wont allow me to specify a default value/previous assignment for a wire. This causes the Verilog generation to be different than the SpinalHDL one (to a degree and edge case). I wanted to put it here to discuss if that is wanted behavior or not in SpinalHDL.
Consider following component (i havent made it "minimal" so forgive me for that but its not big anyway):
So the key thing here is that the
CombOperation
enum is not a power of 2 amount of elements (for the enums with 2^n many elements this probably doesnt apply).With SpinalHDL 1.7.3 I cannot have either of the commented statements in the
aluArea
without SpinalHDL forbidding me to generate the Verilog.In the current form SpinalHDL 1.7.3 generates following Verilog:
As
io_alu_operation
has to be encoded with at least 3 bit there will be some cases in which the circuit wont do anything. I see that SpinalHDL will treat this as "dont care" and probably takes the last "is"-case as the "default". But this is not necessarily obvious to the developer. And since one cannot leave a default statement or a default assignment (for both these commented solutions to the "unobvious behavior" SpinalHDL will generate an error). In the first casetempRes := 0
before the switch statement its ASSIGNMENT OVERLAP, the default statement will cause an UNREACHABLE STATEMENT error.I understand that it makes sense to catch these issues on the elaboration stage, tho without the possibility it might cause unobvious behavior the developer didnt see.
I havent confirmed this yet but I would guess that older SpinalHDL versions allowed me to write the logic like that. Otherwise there is a good chance for a latch.
If I wanted to have some default case there I would need to add another enum value to consider this, giving me another hoop when I wanted to avoid writing by using enum in the first place :P
Or maybe I oversee something then someone ofcourse should correct me :)
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