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Problem with FT232H : 32bits TX (fpga--> PC) 16 upper bits with 16 lower bits switched sometimes after a cold start #9
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64bits transfers same problem 16bits words switched : recv 32 B (increment ok) |
SOLVED !!! For people interested i found one solution to really control the start of your stream in fifo mode. For that I configue ACBUS9 of FT232H chip (UM232H Board) in CBUS Bit Bang Mode. It means i switched ACBUS9 in I/O MODE with FT_ProgUM232H_v3.12.14.633 software (FT232H EEPROM).By default/reset acbus9 start high in I/O mode, so low level will start my stream. And i discover it's possible to combinate SYNC 245 FIFO Mode (usb.setBitMode(0xff, 0x40)) with CBUS Bit Bang Mode (usb.setBitMode(0x??, 0x20)) : you have to use "mode" 0x60 (usb.setBitMode(0x??, 0x20)). So in main code it's something like that : |
And to conclude, thanks a lot to WangXuan!!!! A lot of time saved! good good job! |
Thanks a lot for your sharing! I think your analysis is reasonable: I seem to understand your solution: by treating I'm thinking if there is a way to solve this without additional IO, because you know my repo is designed not only for FT232H but also other FTDI chips such as FT600, so I need to keep the generality. I may consider adding a startup logic inside reg[31:0] counter = 0; Add its reset on line 194: counter <= 0; Modify lines 210~213 and add the logic of waiting for RESET2: begin
{usb_oe, usb_rd, usb_wr} <= '1;
if(counter<6000000) begin
counter <= usb_txe ? 0 : counter+1;
end else begin
stat <= RXIDLE;
end
end If it works, I welcome you to give a PULL REQUEST for this repo, so you can be a contributor. Besides, I welcome you to integrate my repo as a xilinx IP. Any attribution use is welcome. Also, I look forward you to open source your version of AXI-stream and AXI-registers (if there's a major change compared to my repo, there is no need to cite me). |
Hi, Is ok to share, i've already saved a lot of time thanks to you ;) Bytheway, i'm planning to do two mode : a register r/w mode and a stream mode. And like you suggest, i can add a delay-timer for the first transaction in stream mode or use a register dedicated to manage a cold start... I'm planning to submit there what i'll do (if i success ;) )... colin |
Hi,
I copy-past the verilog code inside my fpga. For info i use one UM232H board (FT232H chip) connected with one Digilent CMOD Board (fpga xilinx artix7). 8bits and 16bits transfer working very well from fpga to pc.
For 32 bits i got a strange bug, sometimes (often) i got a switch between the 16 lower bits and the 16 upper bits. It means probably 16bits are lost after a cold start... I found a solution that is to release an hardware reset signal (added to the verilog code) just after started the python sample code.
For exemple (python console) :
WORKING (increment well) :
recv 4 words
0: 0x0174_b082
1: 0x0174_b083
2: 0x0174_b084
3: 0x0174_b085
NOT WORKING (switch 16bits, increment the upper 16bits) :
recv 4 words
0: 0xb0486_0178
1: 0xb0487_0178
2: 0xb0488_0178
3: 0xb0489_0178
This bug is quite strange coz the verilog code in 32bit transfer use two 32bits fifo and one 8bits fifo for the output (where are the 16bits words)
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