Cannot select and cutpoint blackbox modules

[RCoeurjoly]

Version

Yosys 0.44+39 (git sha1 32d770d64, g++ 13.2.0 -Og -fPIC)

On which OS did this happen?

Linux

Reproduction Steps

read_verilog <<EOT
(* blackbox *)
module passthrough(
    input wire in,  // Input signal
    output wire out // Output signal
);

    // Assign the output to be the same as the input
    assign out = in;

endmodule
EOT
cutpoint =*

I get:

2. Executing CUTPOINT pass.

Note that if the module is not a blackbox:

read_verilog <<EOT
module passthrough(
    input wire in,  // Input signal
    output wire out // Output signal
);

    // Assign the output to be the same as the input
    assign out = in;

endmodule
EOT

cutpoint =*

2. Executing CUTPOINT pass.
   Making all outputs of module passthrough cut points, removing module contents.

Expected Behavior

2. Executing CUTPOINT pass.
   Making all outputs of module passthrough cut points, removing module contents.

Actual Behavior

2. Executing CUTPOINT pass.

[RCoeurjoly]

I prepend = to the pattern because the help tells so:

By default, patterns will not match black/white-box modules or their
contents. To include such objects, prefix the pattern with '='.

And it seems that it is correct because we get to here:
https://github.com/YosysHQ/yosys/blob/main/passes/cmds/select.cc#L772