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Excessive recursion in simple program #4598

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joaovam opened this issue Sep 12, 2024 · 2 comments
Open

Excessive recursion in simple program #4598

joaovam opened this issue Sep 12, 2024 · 2 comments
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@joaovam
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joaovam commented Sep 12, 2024

Version

Yosys 0.45+106 (git sha1 982fade, clang++ 14.0.0-1ubuntu1.1 -fPIC -O3)

On which OS did this happen?

Linux

Reproduction Steps

Program used:

localparam id_1 = id_1;
module module_0 (
    output logic id_1,
    id_2,
    inout id_6
);
  assign id_2 = id_6;
endmodule

Command:

yosys -p 'read -sv program.v; hierarchy -check'

Expected Behavior

I believe the program should not be accepted by yosys frontend, since in the declaration localparam id_1 = id_1 id_1 does not exist and is not within a module, causing a loop in the simplifier.

Actual Behavior

 /----------------------------------------------------------------------------\
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |  Copyright (C) 2012 - 2024  Claire Xenia Wolf <claire@yosyshq.com>         |
 |  Distributed under an ISC-like license, type "license" to see terms        |
 \----------------------------------------------------------------------------/
 Yosys 0.45+106 (git sha1 982fade0d, clang++ 14.0.0-1ubuntu1.1 -fPIC -O3)

-- Running command `read -sv program.v; hierarchy -check' --

1. Executing Verilog-2005 frontend: program.v
Parsing SystemVerilog input from `program.v' to AST representation.
Storing AST representation for module `$abstract\module_0'.
Successfully finished Verilog frontend.

2. Executing HIERARCHY pass (managing design hierarchy).

2.1. Executing AST frontend in derive mode using pre-parsed AST for module `\module_0'.
Generating RTLIL representation for module `\module_0'.
Warning: Deep recursion in AST simplifier.
Does this design contain overly long or deeply nested expressions, or excessive recursion?
Segmentation fault
@joaovam joaovam added the pending-verification This issue is pending verification and/or reproduction label Sep 12, 2024
@widlarizer widlarizer added bug and removed pending-verification This issue is pending verification and/or reproduction labels Sep 12, 2024
@widlarizer
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widlarizer commented Sep 12, 2024

Reproduced.

valgrind ./yosys -p "read -noverific; read -sv 4598.v; dump -o 4598.il" doesn't crash and gives us

autoidx 1

attribute \cells_not_processed 1
attribute \src "garbage/4598.v:2.1-8.10"
module $abstract\module_0
end

Then, using that dump, valgrind ./yosys -p "read_rtlil 4598.il; hierarchy -check" doesn't crash and gives us ERROR: Module `$abstract\module_0' is used with parameters but is not parametric!

@whitequark
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Whenever dump gives you $abstract anything, the dump is invalid and can't be used as a reproducer. As I've said many times before, either write_rtlil or read_rtlil should reject such cells.

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