VCD file parsing error in sim pass with GHDL-generated VCDs due to whitespace handling

[RCoeurjoly]

Version

Yosys 0.45+139 (git sha1 e7fc1b0cc, g++ 13.2.0 -fPIC -O3)

On which OS did this happen?

Linux

Reproduction Steps

Given the following VHDL design (vector_assign.vhd):

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity vector_assign is
    Port ( 
        a : in  std_ulogic_vector(3 downto 0);
        b : out std_ulogic_vector(3 downto 0)
    );
end vector_assign;

architecture Behavioral of vector_assign is
begin
    b <= a;
end Behavioral;

And the following test bench (tb.vhd):

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity tb is
end tb;

architecture Behavioral of tb is
    component vector_assign
        Port (
            a : in  std_ulogic_vector(3 downto 0);
            b : out std_ulogic_vector(3 downto 0)
        );
    end component;

    signal a : std_ulogic_vector(3 downto 0) := (others => '0');
    signal b : std_ulogic_vector(3 downto 0);

begin
    uut: vector_assign
        Port map (
            a => a,
            b => b
        );

    stimulus: process
    begin
        a <= "0001";
        wait for 10 ns;
        wait;
    end process;
end Behavioral;

When we create a VCD file with the following script:

ghdl -a vector_assign.vhd

ghdl -a tb.vhd

ghdl -e tb

ghdl -r tb --vcd=ghdl_simulation.vcd

If we elaborate the VHDL design (vector_assign.vhd) and load the GHDL generated VCD with the following yosys script:

verific -vhdl2019 vector_assign.vhd
verific -import vector_assign
sim -vcd yosys_simulation.vcd -n 1
sim -r ghdl_simulation.vcd -scope tb.uut

We get the following error:

3. Executing SIM pass (simulate the circuit).
   Exec: vcd2fst tests/verific/ghdl_simulation.vcd /tmp/nix-shell.eo1ehB/converted_ghdl_simulation.fst
   Warning: Unable to find wire tb.uut.a in input file.
   Warning: Unable to find wire tb.uut.b in input file.
   <suppressed ~4 debug messages>
   ERROR: Unable to find required 'tb.uut.a' signal in file

Preliminary analysis

The VCD declarations of the variables differ:
yosys VCD (yosys_simulation.vcd):
$var wire 4 n1 a [3:0] $end

GHDL VCD (ghdl_simulation.vcd):
$var reg 4 ! a[3:0] $end

The lack of white space between the variable a and the bit range ([3:0]) is the issue.
Note gtkwave loads both VCDs without issue and they are equivalent.

The specification of VCD (See 21.7.2.1 Syntax of 4-state VCD file in IEEE Std 1800™-2017) seems to allow both ways of $var specification.

The relevant function is FstData::extractVarNames in https://github.com/YosysHQ/yosys/blob/main/kernel/fstdata.cc#L112.

Expected Behavior

3. Executing SIM pass (simulate the circuit).
   Exec: vcd2fst tests/verific/ghdl_simulation_edited.vcd /tmp/nix-shell.eo1ehB/converted_ghdl_simulation_edited.fst
   Co-simulation from 0fs to 10000000fs
   Co-simulating sample 0 [0fs].
   Co-simulating sample 1 [10000000fs].

Actual Behavior

3. Executing SIM pass (simulate the circuit).
   Exec: vcd2fst tests/verific/ghdl_simulation.vcd /tmp/nix-shell.eo1ehB/converted_ghdl_simulation.fst
   Warning: Unable to find wire tb.uut.a in input file.
   Warning: Unable to find wire tb.uut.b in input file.
   <suppressed ~4 debug messages>
   ERROR: Unable to find required 'tb.uut.a' signal in file