Use correct offsets in testbench

Signed-off-by: Alex Forencich <alex@alexforencich.com>
alexforencich · Jun 23, 2023 · d730369 · d730369
1 parent 2f881e1
commit d730369
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Showing 3 changed files with 6 additions and 6 deletions.
diff --git a/example/common/tb/example_core_pcie_ptile/test_example_core_pcie_ptile.py b/example/common/tb/example_core_pcie_ptile/test_example_core_pcie_ptile.py
@@ -590,14 +590,14 @@ async def run_test(dut):
     size = 8+64
     stride = 0
     for count in range(8, 256+1, 8):
-        await dma_cpl_buf_test(tb, dev, mem_base, region_len-1, size, stride, count, 2000)
+        await dma_cpl_buf_test(tb, dev, mem_base+128-8, region_len-1, size, stride, count, 2000)
 
     tb.log.info("Test RX completion buffer (CPLH, 8+128+8)")
 
     size = 8+128+8
     stride = 0
     for count in range(8, 256+1, 8):
-        await dma_cpl_buf_test(tb, dev, mem_base, region_len-1, size, stride, count, 2000)
+        await dma_cpl_buf_test(tb, dev, mem_base+128-8, region_len-1, size, stride, count, 2000)
 
     tb.log.info("Test RX completion buffer (CPLD)")
 

diff --git a/example/common/tb/example_core_pcie_s10/test_example_core_pcie_s10.py b/example/common/tb/example_core_pcie_s10/test_example_core_pcie_s10.py
@@ -538,14 +538,14 @@ async def run_test(dut):
     size = 8+64
     stride = 0
     for count in range(8, 256+1, 8):
-        await dma_cpl_buf_test(tb, dev, mem_base, region_len-1, size, stride, count, 2000)
+        await dma_cpl_buf_test(tb, dev, mem_base+128-8, region_len-1, size, stride, count, 2000)
 
     tb.log.info("Test RX completion buffer (CPLH, 8+128+8)")
 
     size = 8+128+8
     stride = 0
     for count in range(8, 256+1, 8):
-        await dma_cpl_buf_test(tb, dev, mem_base, region_len-1, size, stride, count, 2000)
+        await dma_cpl_buf_test(tb, dev, mem_base+128-8, region_len-1, size, stride, count, 2000)
 
     tb.log.info("Test RX completion buffer (CPLD)")
 

diff --git a/example/common/tb/example_core_pcie_us/test_example_core_pcie_us.py b/example/common/tb/example_core_pcie_us/test_example_core_pcie_us.py
@@ -631,14 +631,14 @@ async def run_test(dut):
     size = 8+64
     stride = 0
     for count in range(8, 256+1, 8):
-        await dma_cpl_buf_test(tb, dev, mem_base, region_len-1, size, stride, count, 2000)
+        await dma_cpl_buf_test(tb, dev, mem_base+128-8, region_len-1, size, stride, count, 2000)
 
     tb.log.info("Test RX completion buffer (CPLH, 8+128+8)")
 
     size = 8+128+8
     stride = 0
     for count in range(8, 256+1, 8):
-        await dma_cpl_buf_test(tb, dev, mem_base, region_len-1, size, stride, count, 2000)
+        await dma_cpl_buf_test(tb, dev, mem_base+128-8, region_len-1, size, stride, count, 2000)
 
     tb.log.info("Test RX completion buffer (CPLD)")