Updating submodules.

 * litedram changed from 8a46b71 to 87578dd
    *   87578dd - Merge pull request timvideos#153 from antmicro/jboc/issue-151 <enjoy-digital>
    |\
    | * 19cbf7d - test/benchmarks: add memtype to summary (timvideos#151) <Jędrzej Boczar>
    * |   4f9d6e4 - Merge pull request timvideos#152 from antmicro/jboc/benchmark <enjoy-digital>
    |\ \
    | * | a5d2c09 - test: add benchmark timeout parameter <Jędrzej Boczar>
    | |/
    * |   99e5356 - Merge pull request timvideos#150 from antmicro/jboc/latency-sorting <enjoy-digital>
    |\ \
    | * | 247722d - test: fix wrong sorting in benchmarks summary <Jędrzej Boczar>
    | |/
    * | 07d2483 - litedram_gen: Limit SDRAM size exposed to the CPU to 16MB. <Florent Kermarrec>
    * | 53d3a0a - litedram_gen: cleanup ident/align, use dynamic CSRs. <Florent Kermarrec>
    * | f1dba78 - frontend/dma/LiteDRAMDMAWriter/add_csr: add missing sink.valid <Florent Kermarrec>
    * | ebaf612 - Merge pull request timvideos#148 from antmicro/jboc/benchmark <enjoy-digital>
    |\|
    | * a278411 - test: option to print heartbeat during benchmarks to avoid Travis timeouts <Jędrzej Boczar>
    |/
    *   5fb2b01 - Merge pull request timvideos#146 from antmicro/jboc/benchmark <enjoy-digital>
    |\
    | * d142541 - test: run benchmarks in Travis CI and deploy the results <Jędrzej Boczar>
    | * b7ed91d - test: suppress info log messages in benchmark runner <Jędrzej Boczar>
    | * c6cc0e0 - test: keep benchmark failures in data frame and filter out when needed <Jędrzej Boczar>
    | * bba49f2 - test: add generation of html benchmarks summary <Jędrzej Boczar>
    * |   24d33d1 - Merge pull request timvideos#144 from antmicro/sdram-verbosity-benchmark <enjoy-digital>
    |\ \
    | * | f0be039 - test: add option to use sdram timing verifier in benchmarks <Piotr Binkowski>
    * | |   878b586 - Merge pull request timvideos#143 from antmicro/addressing-fix <enjoy-digital>
    |\ \ \
    | |/ /
    |/| |
    | * | ef0086e - phy/model: fix memory addressing issues in some configurations <Piotr Binkowski>
    | |/
    * | 5719b77 - phy: use new BitSlip module with reduced latency (-1 sys_clk cycle) <Florent Kermarrec>
    * | d646e2a - common: add BitSlip module (with reduced latency) <Florent Kermarrec>
    |/
    * 9083822 - phy/model: change timing checker parameter, use a verbosity parameter <Florent Kermarrec>
    *   95b827d - Merge pull request timvideos#142 from antmicro/updated-trefi-verifier <enjoy-digital>
    |\
    | * 13d0350 - phy/model: add refresh postponing checks <Piotr Binkowski>
    | * 93e2207 - phy/model: check tREFI in 64ms time slices <Piotr Binkowski>
    * 0ba31d6 - frontend/bist: regroup random_data/random_addr in the same CSRStorage to keep software retro-compatibility <Florent Kermarrec>
    * fc27b21 - frontend/bist: fix LiteDRAMBISTChecker random_data/addr <Florent Kermarrec>
    * e0b4278 - frontend/bist: set run to 1 by default to keep similar default behaviour than before adding run/ready. <Florent Kermarrec>

 * liteeth changed from f532a12 to 466223e
    * 466223e - liteeth/gen: update copyrights <Florent Kermarrec>
    *   d6b5888 - Merge pull request timvideos#34 from Xiretza/generator-improvements <enjoy-digital>
    |\
    | * 7a44209 - Make memory/CSR regions customizable in config <Xiretza>
    | * ca9cbd1 - Move more options to config file <Xiretza>
    | * eea1086 - Use builder arguments in generator <Xiretza>
    | * b9fb1f0 - Remove leftover classes in generator <Xiretza>
    |/
    * 358bc23 - examples/.ymls: add separators <Florent Kermarrec>
    * ddcbc33 - test/test_gen: update <Florent Kermarrec>
    * fcadd60 - liteeth/gen: initial switch to YAML config file (similar to LiteDRAM/LitePCIe) <Florent Kermarrec>
    *   b029088 - Merge branch 'ximinity-generator-lattice' <Florent Kermarrec>
    |\
    | * 0954fa3 - Merge branch 'generator-lattice' of git://github.com/ximinity/liteeth into ximinity-generator-lattice <Florent Kermarrec>
    |/|
    | * ae10eea - gen: add lattice support <Stefan Schrijvers>
    * |   fcf7b24 - Merge pull request timvideos#33 from Xiretza/standalone-features <enjoy-digital>
    |\ \
    | * | 5767dfc - Honour --output-dir argument in generator <Xiretza>
    | * | 153c160 - Prioritise overridden interrupts and memory regions <Xiretza>
    | * | ec9bc57 - Fix MII tx_en signal width in standalone generator <Xiretza>
    | * | 42a7b6c - Allow little-endian interface for standalone design <Xiretza>
    | * | a696ccd - Expose interrupt pin for standalone design <Xiretza>
    |/ /
    * | 208bc09 - liteeth/gen: update <Florent Kermarrec>
    * | ddd0431 - examples: use integrated sram instead of external one. (Also fix regression with new SoC that no longer support address decoders passed to add_wb_slave) <Florent Kermarrec>
    |/
    * 081bf46 - mac/sram: simplify code and improve SRAM read speed using async_read on Memory. <Florent Kermarrec>
    * bf4a11a - mac/sram: simplify counter (use NextValue in FSM) <Florent Kermarrec>
    * 721238b - mac/sram: cosmetic changes <Florent Kermarrec>

 * litepcie changed from 061418c to be68cba
    * be68cba - common/get_bar_mask: cleanup indent <Florent Kermarrec>
    * 03fba67 - phy/s7pciephy: add AXISRX128BAligner for 128-bit pcie_data_width case. <Florent Kermarrec>
    * 9768cb3 - phy/s7pciephy: add assertions on nlanes, data_width, pcie_data_width <Florent Kermarrec>
    * aad83e1 - phy/s7pciephy: add pcie_data_width support and add back pcie_data_width=128 support <Florent Kermarrec>
    * 1d69a27 - core/msi: generate MSI only if enable (fixes issue seen on an AMD Ryzen configuration) <Florent Kermarrec>

 * litevideo changed from 49bafa4 to 146d4a7
    *   146d4a7 - Merge pull request timvideos#26 from FrankBuss/master <enjoy-digital>
    |\
    | * 7c24d18 - minor comments and example code cleanup <fb@frank-buss.de>
    |/
    * 7328d27 - terminal/core: remove obsolete vsync definition <Florent Kermarrec>
    * ab06562 - terminal: remove vga_clk parameter (a vga clock domain should exist in the SoC), add pads parameter and use it for hsync/vsync/r/g/b if Not None. <Florent Kermarrec>
    *   69e0757 - Merge pull request timvideos#25 from FrankBuss/master <enjoy-digital>
    |\
    | * 6d1831e - added missing files when installing it with "pip3 install ." <fb@frank-buss.de>
    |/
    * cb73fe9 - terminal/README: update <Florent Kermarrec>
    * 73ee69f - terminal/core: uniformize style with the others cores <Florent Kermarrec>
    * 31761ce - terminal/core: give more explict name to clk/clock_domain (vga_clk/cd_vga) <Florent Kermarrec>
    * 5e70963 - terminal/core: avoid exposing internal signals <Florent Kermarrec>
    * 9742f8a - Merge pull request timvideos#24 from FrankBuss/master <enjoy-digital>
    * 2ce9008 - VGA terminal emulation <fb@frank-buss.de>

 * litex changed from 02bfda5e to 485934ed
    * 485934ed - doc/socdoc: fix example <Florent Kermarrec>
    * 53ee9a5e - cpu/blackparrot: first cleanup pass <Florent Kermarrec>
    * f3829cf0 - integration/soc: set base_address on LiteDRAMWishbone2Native, fix addressing with >= 1GB SDRAMs. <Florent Kermarrec>
    * 3a6f97ff - build/sim: add Verilator FST tracing support. <Florent Kermarrec>
    *   8a715f3b - Merge pull request timvideos#390 from gsomlo/gls-add-sdcard <enjoy-digital>
    |\
    | * 516cf405 - targets/nexys4ddr: add optional sdcard support <Gabriel Somlo>
    | * d4d2b7f7 - bios: add litesdcard test routines to boot menu <Gabriel Somlo>
    | * 7a2e33b8 - targets/nexys4ddr: add ethernet via method instead of inheritance <Gabriel Somlo>
    |/
    * 774a55a2 - soc_core: fix missing init on main_ram <Florent Kermarrec>
    *   5d580ca4 - Merge pull request timvideos#389 from antmicro/linux_flash_offsets <enjoy-digital>
    |\
    | * 659c244a - bios/boot: allow to customize flash offsets of Linux images <Mateusz Holenko>
    * | 00895518 - cores/cpu: use standard+debug variant when only debug is specified. <Florent Kermarrec>
    |/
    * ae45be47 - soc/cores/clock: add reset_cycles parameter to S7IDELAYCTRL/USIDELAYCTRL <Florent Kermarrec>
    * 9baa3ad5 - soc/csr_bus: fix aligned_paging computation (should be done with SoC's Bus data width not bus.alignment) <Florent Kermarrec>
    * 854e7cc9 - integration/soc: improve Region logger <Florent Kermarrec>
    * 9cb8f68e - bios/boot: update and fix flashboot, improve verbosity <Florent Kermarrec>
    * 6ed0f445 - soc: increase supporteds address_width/paging <Florent Kermarrec>
    * 5b3808cb - soc_core: expose CSR paging <Florent Kermarrec>
    * 0497f3ca - soc/csr_bus: improve CSR paging genericity <Florent Kermarrec>
    * 351896bf - tools/litex_sim: use new sdram verbosity parameter <Florent Kermarrec>
    * 67e8a042 - integration/soc: add configurable CSR Paging <Florent Kermarrec>
    * 65764701 - soc_core: add back identifier <Florent Kermarrec>
    *   8f6114d0 - Merge pull request timvideos#387 from BracketMaster/master <enjoy-digital>
    |\
    | * 3da204ed - update to work with mac <Yehowshua Immanuel>
    * | 3574b909 - tools/litex_sim: specify default local/remote-ip addresses. <Florent Kermarrec>
    * | aebaea77 - tools/litex_sim: add ethernet local/remote-ip arguments. <Florent Kermarrec>
    |/
    * 18a9d4ff - interconnect/stream: cleanup imports/idents <Florent Kermarrec>
    *   57fb3720 - Merge pull request timvideos#386 from antmicro/sdram-timing-checker <enjoy-digital>
    |\
    | * eff85a99 - tools/litex_sim: add cli options to control SDRAM timing checker <Piotr Binkowski>
    |/
    * e4712ff7 - soc_core: fix cpu_variant renaming regression <Florent Kermarrec>
    * a2f1683b - doc: rename lxsocdoc -> socdoc and update readme <Sean Cross>
    * baa29f1b - doc: fix regression with new irq manager <Sean Cross>
    * 1620f9c5 - soc/CSR: show alignment in report and add info when updating. <Florent Kermarrec>
    * 5b34f4cd - soc/add_cpu: use cpu.data_width as CSR alignment, fix regression on Rocket <Florent Kermarrec>
    * 2f69f607 - integration/soc: fix refactoring issues <Florent Kermarrec>
    * 1d6ce66b - soc/integration/builder: update copyright, align arguments <Florent Kermarrec>
    *   98ae91ad - Merge pull request timvideos#383 from Xiretza/builder-directories <enjoy-digital>
    |\
    | * b5654579 - Unify output directory handling in builder <Xiretza>
    |/
    *   4a15c3e2 - Merge pull request timvideos#382 from enjoy-digital/new_soc <enjoy-digital>
    |\
    | * e9c665a5 - soc_core/soc_sdram: add disclaimer <Florent Kermarrec>
    | * 5558865c - soc_core: provide full retro-compatibily when add_wb_slave is called before add_memory_region <Florent Kermarrec>
    | * 1b5caf56 - soc: fix busword typo <Florent Kermarrec>
    | * 8b5cc345 - targets/EthernetSoC: be sure memory region is added before adding Wishbone Slave (required by new SoC) <Florent Kermarrec>
    | *   240a55ba - Merge branch 'master' into new_soc <enjoy-digital>
    | |\
    | |/
    |/|
    * | d5ad1d56 - soc/integration: move mem_decoder to soc_core <Florent Kermarrec>
    * | 0a737cb6 - soc/integration/common: simplify get_version <Florent Kermarrec>
    * | 4d761e1a - cores/cpu: remove separators on io_regions (requires python 3.6) <Florent Kermarrec>
    * |   7c57a33b - Merge pull request timvideos#380 from Xiretza/cpunone-all-io <enjoy-digital>
    |\ \
    | * | e301df7f - Allow all memory regions to be used as IO with CPUNone <Xiretza>
    |/ /
    * | 16d1972b - integration/common: fix mem_decoder (shadow base has been deprecated) <Florent Kermarrec>
    * | 7ee9ce38 - .gitmodules/black-parrot: switch to https://github.com/enjoy-digital/black-parrot (without the submodules) <Florent Kermarrec>
    * |   1dced818 - Merge pull request timvideos#278 from scanakci/blackparrot_litex <enjoy-digital>
    |\ \
    | * | d15c911c - BlackParrot initial commit w/ Litex BIOS simulation including LiteDRAM w/ Litex BIOS working on FPGA excluding LiteDRAM <sadullah>
    * | | 1d70ef69 - soc/cores/spi_opi: cleanup, rename to S7SPIOPI (since 7-Series specific for now) <Florent Kermarrec>
    * | | 62f3537d - soc/cores: rename spiopi to spi_opi <Florent Kermarrec>
    * | | f58e8188 - soc/cores/i2s: cleanup pass, rename to S7I2SSlave (since 7-Series specific for now), rename fifodepth to fifo_depth for consistency with others cores. <Florent Kermarrec>
    * | |   c2c80b5d - Merge pull request timvideos#378 from betrusted-io/merge_ip <enjoy-digital>
    |\ \ \
    | * | | 98e46c27 - reduce indents <bunnie>
    | * | | d2b394a9 - update doc comments on events for i2s <bunnie>
    | * | | 416afd31 - add doc comment for event <bunnie>
    | * | | 33d9e45a - fix formatting on spiopi <bunnie>
    | * | | cc6ed667 - Request to merge I2S and SPIOPI cores <bunnie>
    | | | * 399b65fa - soc/add_uart: fix bridge <Florent Kermarrec>
    | | | * 160c55d1 - soc_core/soc_sdram: remove disclaimer (we'll add it later when designs will be adapted) <Florent Kermarrec>
    | | | * b2c66b1e - soc: avoid double definition of main_ram <Florent Kermarrec>
    | | | * 5f994608 - soc: improve log colors on error reporting <Florent Kermarrec>
    | | | * b22d2ca0 - soc: add linker regions management <Florent Kermarrec>
    | | | * abc31a92 - soc: improve log presentation/colors <Florent Kermarrec>
    | | | * 91e2797b - soc: fix cpu_reset_address <Florent Kermarrec>
    | | | * 0d7430fc - tools/litex_sim_new: remove <Florent Kermarrec>
    | | | * 21d38701 - soc: fix build_time format <Florent Kermarrec>
    | | | * b43d830f - soc/add_sdram: simplify L2 Cache, use FullMemoryWE on L2 Cache by default (seems better on all devices) <Florent Kermarrec>
    | | | * ea8e745a - soc_core/common: move old mem_decoder to soc_core, simplify get_version <Florent Kermarrec>
    | | | * 5e11e839 - tools/litex_sim_new: switch to dynamically allocated ethmac origin <Florent Kermarrec>
    | | | * dd0c71d7 - soc/SoCRegion/Decoder: pass bus to decoder and remove mask on origin <Florent Kermarrec>
    | | | * e8e4537e - soc/add_sdram: avoid L2 cache when l2_cache_size == 0. <Florent Kermarrec>
    | | | * dcbdb732 - soc: remove unneeded \n <Florent Kermarrec>
    | | | * 0f1811fb - tools/litex_sim_new: use new bus/csr/irq methods <Florent Kermarrec>
    | | | * d320be8e - soc: use io_regions for alloc_region <Florent Kermarrec>
    | | | * 9ac09ddd - tools: add litex_sim_new based on SoCCore and using add_sdram method <Florent Kermarrec>
    | | | * cbcd953d - soc_core: use add_rom <Florent Kermarrec>
    | | | * 487ac3da - soc/add_cpu: simplify CPUNone integration <Florent Kermarrec>
    | | | * f7d4648c - soc/SoCBusHandler: add add_adapter method and use it to convert Master/Slave before connecting to the Bus <Florent Kermarrec>
    | | | * 379d47a8 - soc/add_sdram: add sdram csr <Florent Kermarrec>
    | | | * 3921b634 - soc/add_sdram: fix rocket, shorten comments <Florent Kermarrec>
    | | | * 14b627b4 - soc/add_sdram: improve API <Florent Kermarrec>
    | | | * 1faefdc0 - soc: add LiteXSoC class and mode add_identifier/uart/sdram to it <Florent Kermarrec>
    | | | * 11dbe190 - soc_core/sdram: cleanup, add disclaimer <Florent Kermarrec>
    | | | * 5eb88cd9 - soc: add add_sdram <Florent Kermarrec>
    | | | * 39011593 - soc: add csr_regions, update copyright <Florent Kermarrec>
    | | | * d2b06951 - soc: add cpu rom/sram check <Florent Kermarrec>
    | | | * de100fdd - soc: add SOCIORegion and manage it <Florent Kermarrec>
    | | | * 6b8c425f - soc: reorder main components/peripherals <Florent Kermarrec>
    | | | * 84b5df78 - soc: add add_cpu method <Florent Kermarrec>
    | | | * b676a559 - soc: fix unit-tests <Florent Kermarrec>
    | | | * 0a588390 - soc: integrate constants/build <Florent Kermarrec>
    | | | * 014d5a56 - soc: show sorted regions (by origin) / locs <Florent Kermarrec>
    | | | * c69b6b7c - soc: simplify color theme <Florent Kermarrec>
    | | | * 3cb90297 - soc: add add_uart method <Florent Kermarrec>
    | | | * e5cacb8b - soc_core: cleanup imports <Florent Kermarrec>
    | | | * 33d498b8 - soc_core: get_csr_address no longer used <Florent Kermarrec>
    | | | * 1feff1d7 - soc: integrate CSR master/interconnect/collection and IRQ collection <Florent Kermarrec>
    | | | * 3ba7c29e - soc: add add_constant/add_config methods <Florent Kermarrec>
    | | | * 29bbe4c0 - soc: add add_csr_bridge method <Florent Kermarrec>
    | | | * b84c291c - soc: add add_controller/add_identifier/add_timer methods <Florent Kermarrec>
    | | | * 9445c33e - soc: add add_ram/add_rom methods <Florent Kermarrec>
    | | | * e5a8ac1d - soc: add automatic bus data width convertion to add_master/add_slave <Florent Kermarrec>
    | | | * 8f67f115 - soc/soc_core: cleanup, remove some unused attributes <Florent Kermarrec>
    | | | * 2c6e5066 - soc: move SoCController from soc_core to soc <Florent Kermarrec>
    | | | * 848fa20d - soc: create SoCLocHandler and use it to simplify SoCCSRHandler and SoCIRQHandler <Florent Kermarrec>
    | | | * 39458c92 - soc: add use_loc_if_exists on SoCIRQ.add to use current location is already defined <Florent Kermarrec>
    | | | * 1eff0799 - soc: add use_loc_if_exists on SoCCSR.add to use current location is already defined <Florent Kermarrec>
    | | | * 8bc42067 - soc/integration: initial adaptation to new SoC class <Florent Kermarrec>
    | | | * 6baa07a6 - soc/integration: add new soc class prorotype with SoCRegion/SoCBus/SoCCSR/SoCIRQ/SoC <Florent Kermarrec>
    | |_|/
    |/| |
    * | | 9b11e919 - cpu/vexriscv: update submodule <Florent Kermarrec>
    |/ /
    * | ae085782 - doc: add lxsocdoc.md (README from lxsocdoc repository) <Sean Cross>
    * |   5ff02e23 - Merge pull request timvideos#375 from xobs/add-lxsocdoc <enjoy-digital>
    |\ \
    | * | 58598d4f - integration: svd: move svd generation to `export` <Sean Cross>
    | * | 73ed7e56 - soc: doc: use sphinx toctree as it was intended <Sean Cross>
    | * | 7c3bc0b0 - litex-doc: initial merge of lxsocdoc <Sean Cross>
    * | | 1944d8d9 - bios/main: add LiteX tagline <Florent Kermarrec>
    * | |   40cddca9 - Merge pull request timvideos#376 from antmicro/build-sim-do-not-override-C-LD-FLAGS <enjoy-digital>
    |\ \ \
    | |/ /
    |/| |
    | * | 90fe5850 - build/sim: allow to use environment's {C,LD}FLAGS <Mariusz Glebocki>
    |/ /
    * |   bd6fd3da - Merge pull request timvideos#373 from antmicro/l2-reverse <enjoy-digital>
    |\ \
    | * | f3b068e2 - tools/litex_sim: use l2_reverse flag <Piotr Binkowski>
    |/ /
    * | 3350d33f - wishbone/Cache: add reverse parameter <Florent Kermarrec>
    * | eff9caee - soc_sdram: add l2_reverse parameter <Florent Kermarrec>
    * |   6e5b47f4 - Merge pull request timvideos#370 from Disasm/fixes <enjoy-digital>
    |\ \
    | * | de88ed28 - Fix argument descriptions <Vadim Kaushan>
    | * | eb49ec21 - Pass --csr-json to the Builder <Vadim Kaushan>
    |/ /
    * | b69f2993 - soc_core: add UART bridge support (simplify having to do it externally) <Florent Kermarrec>
    * | 7a6c04db - build/altera/quartus: fix fmt_r typo <Florent Kermarrec>
    * | c6b9676d - cpu/minerva: update (use new nMigen API) <Florent Kermarrec>
    * | 9d289472 - inteconnect/stream: use PipeValid implementation for Buffer <Florent Kermarrec>
    * | 1c88c0f8 - inteconnect/stream: cleanup <Florent Kermarrec>
    * |   cafd9c35 - Merge pull request timvideos#366 from gsomlo/gls-csr-followup <enjoy-digital>
    |\ \
    | * | ff2775c2 - software, integration/export: (re-)expose CSR subregister accessors <Gabriel Somlo>
    * | | f3f9808d - interconnect/stream: add PipeValid and PipeWait to cut timing paths. <Florent Kermarrec>
    * | | b22ad1ac - build/xilinx/vivado: improve readability of generated tcl/xdc files <Florent Kermarrec>
    |/ /
    * | 7bc34a9b - integration/soc_core: revert integrate_sram_size default value (cause issues when using External SPRAM). <Florent Kermarrec>
    * |   b4b56db4 - Merge pull request timvideos#363 from antmicro/litex-sim-ddr4 <enjoy-digital>
    |\ \
    | * | c02dd5e8 - tools/litex_sim: add ddr4 PhySettings <Piotr Binkowski>
    |/ /
    * | 0820adbd - tools/litex_sim: add --sdram-init parameter <Florent Kermarrec>
    * | 01ae10b8 - software/bios: revert M-Labs MiSoC copyright. <Florent Kermarrec>
    * | ea5ef8c1 - README: update copyright year and make sure LICENSE/README both mention MiSoC <Florent Kermarrec>
    * | 95cfa6a8 - platforms/netv2: add pcie pins <Florent Kermarrec>
    * |   f9bc98ed - Merge pull request timvideos#359 from gregdavill/bios_ddr3_ecp5 <enjoy-digital>
    |\ \
    | * | 1f439062 - soc/software/bios/sdram: ECP5 move strobe dly_sel <Greg Davill>
    | * | f84f57d6 - soc/software/bios/sdram: On ECP5 strobe dly_sel after read leveling <Greg Davill>
    |/ /
    * | 52765488 - tools/litex_sim: update copyrights and cosmetic changes <Florent Kermarrec>
    * |   b280bb2f - Merge pull request timvideos#358 from antmicro/litex_sim_ddr <enjoy-digital>
    |\ \
    | * | 9aa97c2e - tools/litex_sim: add support for other sdram types (DDR, LPDDR, DDR2, DDR3) <Piotr Binkowski>
    * | | 19ef19ce - cores/clock/create_clkout: rename clk_ce to ce, improve error reporting <Florent Kermarrec>
    * | |   7e088360 - Merge pull request timvideos#357 from betrusted-io/add_clk_ce <enjoy-digital>
    |\ \ \
    | |/ /
    |/| |
    | * | 1f7549b4 - add BUFIO to clockgen buffer options <bunnie>
    | * | b3f9aa11 - add option for BUFGCE to the clock generator buffer types <bunnie>
    * | | cbc081c4 - tools/litex_sim: review/cleanup sdram-module/sdram-data-width features. <Florent Kermarrec>
    * | |   b35ea459 - Merge pull request timvideos#354 from antmicro/litex_sim_ddr <enjoy-digital>
    |\ \ \
    | * | | 674cfcde - tools/litex_sim: specify dram chip and data width via commandline <Piotr Binkowski>
    * | | |   b23f13d9 - Merge pull request timvideos#351 from antmicro/fix_sram_size_argument <enjoy-digital>
    |\ \ \ \
    | |/ / /
    |/| | |
    | * | | 7a05353a - soc_core: rename integrated_sram_size argument <Mateusz Holenko>
    | * | | c4bb4169 - soc_core: fix integrated_sram_size argument type <Mateusz Holenko>
    * | | | 5845df76 - build/xilinx/vivado: add pre_placement/pre_routing commands <Florent Kermarrec>
    * | | | 13880882 - cores/icap: add add_timing_constraints method <Florent Kermarrec>
    * | | | 2074a86e - cores/dna: cleanup and add add_timing_constraints method <Florent Kermarrec>
    |/ / /
    * | | d39dc8cf - tools/litex_sim: cleanup/simplify <Florent Kermarrec>
    * | | a0d95766 - build/sim: add -Wl,--no-as-needed to LDFLAGS for Ubuntu 16.04 support (thanks kamejoko80) <Florent Kermarrec>
    * | | 80c3dc41 - targets: use mem_region.origin instead of mem_map definition (prepare for automatic mem_region allocation) <Florent Kermarrec>
    * | | 53bc18cc - soc_core: add new alloc_mem/add_mem_region to allow automatic allocation of memory regions <Florent Kermarrec>
    |/ /
    * | eae0e004 - cores/clock/xadc: ease DRP timings <bunnie>
    * | 7b92a17c - test/test_targets: limit max_sdram_size to 1GB <Florent Kermarrec>
    * | 008a0894 - targets/nexys4ddr: fix typo <Florent Kermarrec>
    * | 36e5274a - SoCSDRAM: set default max_sdram_size to 1GB (maximum we can map with current mem_map) <Florent Kermarrec>
    * | 46c1c5c1 - targets/kcu105: remove main_ram_size_limit <Florent Kermarrec>
    * | 5913c91c - SoCSDRAM: rename main_ram_size_limit to max_sdram_size and make it a parameter of SoCSDRAM, expose SoCSDRAM parameters to user <Florent Kermarrec>
    * | 1c465f89 - build/lattice: add add_false_path_constraint method for API compatibility but false paths are not yet used/translated to .lpf file <Florent Kermarrec>
    * | b4ba2a47 - soc/cores/uart: set rx_fifo_rx_we to True on UARTCrossover <Florent Kermarrec>
    |/
    * 5aa516cb - soc/cores/uart: add rx_fifo_rx_we parameter to pulse rx_fifo.source.ready on rxtx register read. <Florent Kermarrec>
    * 862e784e - cpu/vexriscv: use 32-bit signal for externalResetVector <Florent Kermarrec>
    * f2a1673f - targets/arty/genesys2: fix EthernetSoC/EtherboneSoC selection <Florent Kermarrec>
    * 990870d0 - targets/genesys2: add EtherboneSoC <Florent Kermarrec>
    * 820e79bf - platforms/de0nano: specify gpio for serial <Florent Kermarrec>
    * ba366d42 - targets: cleanup EthernetSoC <Florent Kermarrec>
    * a2685370 - soc/interconnect/packet/Depacketizer: use both sink.valid and sink.ready to update sink_d, fix Etherbone regression on Arty. <Florent Kermarrec>
    * a168ecba - targets/arty: add EtherboneSoC <Florent Kermarrec>
    * 7a4ecfa5 - targets/kcu105: update <Florent Kermarrec>
    * 68e225fb - test/test_targets: update <Florent Kermarrec>
    * 42efa998 - SoCCore: set default integrated_rom/ram_size to 0. For targets, defaults values are provided by soc_core_args. <Florent Kermarrec>
    * 4050e608 - SoCCore: use hex for integrated_rom/sram_size <Florent Kermarrec>
    *   f818755c - Merge pull request timvideos#339 from gsomlo/gls-csr-cleanup <enjoy-digital>
    |\
    | * b073ebad - bios/sdram: switch to updated CSR accessors, and misc. cleanup <Gabriel Somlo>
    | * 2c393041 - software, integration/export: rename and reimplement CSR accessors <Gabriel Somlo>
    * | f1606dbc - tools/litex_sim: use default integrated_rom_size <Florent Kermarrec>
    * | 4648db0c - cores/uart/UARTInterface: remove connect method <Florent Kermarrec>
    * | 6c9f418d - soc_core: fix uart stub <Florent Kermarrec>
    |/
    * 63cd23c9 - cpu/vexriscv: revert mem_map_linux/main_ram <Florent Kermarrec>
    * 83a7225c - SoCCore: set integrated rom/sram size default values in soc_core_args and use it in targets <Florent Kermarrec>
    * 6e3f25a7 - cpu/vexriscv/mem_map_linux: update main_ram to 0x40000000 <Florent Kermarrec>
    * fe14b9cf - targets/genesys2: update self.register_sdram <Florent Kermarrec>
    * 39ce39a2 - soc_sdram: add l2_data_width parameter to set minimal l2_data_width to improve DRAM accesses efficiency. <Florent Kermarrec>
    * 23175190 - cores/uart: add UARTCrossover <Florent Kermarrec>
    * 2f03d323 - cores/uart/UART: add stream interface (phy=None), add connect method and use this for UART Stub/Crossover. <Florent Kermarrec>
    * d92bd8ff - gen/fhdl/verilog: fix signed init values <Florent Kermarrec>
    *   ff066a5e - Merge pull request timvideos#338 from DurandA/master <enjoy-digital>
    |\
    | * d24a4b54 - Add optional 'ignore-loops' flag to nextpnr <Arnaud Durand>
    * | 26fe45fc - cores/uart: rename BridgedUART to UARTEmulator and rework/simplify it. Also integrated it in SoCCore with uart_name="emulator" <Florent Kermarrec>
    * |   d40bf9d8 - Merge pull request timvideos#340 from xobs/bridged-uart <enjoy-digital>
    |\ \
    | |/
    |/|
    | * 5079a3c3 - uart: add BridgedUart <Sean Cross>
    |/
    * f70dd482 - bios/sdram: add memspeed <Florent Kermarrec>
    * fa22d6aa - wishbone/Cache: avoid REFILL_WRTAG state to improve speed. <Florent Kermarrec>
    * f408527d - soc/cores/cpu: add riscv64-linux toolchain support for risc-v cpus. <Florent Kermarrec>
    * 8889821c - targets: sync with litex-boards <Florent Kermarrec>
    * aba8fc5c - build/altera/quartus: allow multiple call of add_period_constraint if constraint is similar. <Florent Kermarrec>
    *   e318287e - Merge pull request timvideos#337 from gregdavill/spi-flash <enjoy-digital>
    |\
    | * 49781467 - soc/cores/spi_flash: Don't tristate DQ2/DQ3 when bitbanging <Greg Davill>
    * | 2cf95e9f - platforms/minispartan6: rename sd to sdcard and regroup data lines <Florent Kermarrec>
    * | e99740e8 - platforms/nexys4ddr: add sdcard pins <Florent Kermarrec>
    * | 83ad674f - build/lattice/trellis: use a single fonction to parse device <Florent Kermarrec>
    * |   018c7ca8 - Merge pull request timvideos#336 from kbeckmann/trellis-speed <enjoy-digital>
    |\ \
    | * | 426ab676 - trellis: Pass speed grade argument to nextpnr <Konrad Beckmann>
    |/ /
    * |   fd4cbd80 - Merge pull request timvideos#331 from betrusted-io/xadc_mods <enjoy-digital>
    |\ \
    | * | 378722a7 - soc/cores/xadc: define analog_layout and simplify analog_pads connections <Florent Kermarrec>
    | * | 87d456ca - bring back analog_pads specifier, remove reset conditions on VP <bunnie>
    | * | 4dc0a614 - soc/core/xadc: cleanup, simplify and add expose_drp method - keep CSR ordering with older version, requested for software compatibility. - always enable analog capability (user will just not use it if not needed). - add expose_drp method (similar to clock.py) for cases where DRP is needed. <Florent Kermarrec>
    | * | 5eec7432 - fix a couple bugs in the DRP readout path <bunnie>
    | * | 56ccaeeb - add support for DRP on XADC <bunnie>
    * | | 642d0737 - cpu/minerva: fix variant syntax warning <Florent Kermarrec>
    * | |   8ba204c7 - Merge pull request timvideos#332 from gsomlo/gls-csr-mem-sel <enjoy-digital>
    |\ \ \
    | * | | d087e2e0 - interconnect/csr_bus/SRAM: allow 64-bit alignment (on 64-bit CPUs) <Gabriel Somlo>
    |/ / /
    * | | 690de79d - cpu/microwatt: reorder sources, add comments <Florent Kermarrec>
    * | | e36df2a6 - build/lattice/icestorm: increase similarities with trellis. <Florent Kermarrec>
    * | | 197edad3 - soc/integration/soc_core/SoCController: specify initial reset value of scratch register in description <Florent Kermarrec>
    * | | b65a36e7 - soc/integration/soc_core/SoCController: rephrase CSR descriptions a bit <Florent Kermarrec>
    * | |   1f27b21f - Merge pull request timvideos#330 from xobs/document-ctrl-timer0 <enjoy-digital>
    |\ \ \
    | * | | c5aa929d - cores: timer: clean up wording for timer documentation <Sean Cross>
    | * | | 2d75aee7 - soc_core: ctrl: document registers <Sean Cross>
    | * | | a251d712 - cores: timer: fix documentation formatting <Sean Cross>
    |/ / /
    * | | db7a48c0 - soc/cores/clock: also allow margin=0 on iCE40PLL and ECP5PLL <Florent Kermarrec>
    * | | caacc411 - Merge pull request timvideos#328 from betrusted-io/precise_clocks <enjoy-digital>
    |\| |
    | * | 219bb7f2 - add the possibility for a "precise" clock solution <bunnie>
    |/ /
    * | 9336fe11 - build/microsemi/libero_soc: update add_period_constraint behavior when clock is already constrainted. <Florent Kermarrec>
    * | 3022f02b - build/xilinx/vivado: update add_period_constraint behavior when clock is already constrainted. <Florent Kermarrec>
    * | fe4eaf58 - build/lattice/icestorm/add_period_constraint: improve <Florent Kermarrec>
    * | 6b91e882 - soc/integration/builder: avoid try/except on LiteDRAM import, just check if SoC has an sdram and do the import if so <Florent Kermarrec>
    * |   2157d0f3 - Merge pull request timvideos#327 from zakgi/master <enjoy-digital>
    |\ \
    | * | 39ae230b - moving RAM offsets outside of CSR_ETHMAC define <Giammarco Zacheo>
    * | | f0b5c672 - Allow specifying the same clock constraint multiple times. <Tim 'mithro' Ansell>
    * | | 8b955e6f - Allow LiteX builder to be used without LiteDRAM. <Tim 'mithro' Ansell>
    * | | a738739a - Improve the invalid CPU type error message. <Tim 'mithro' Ansell>
    * | | 85ade2b3 - build/xilinx/programmer: fix vivado_cmd when settings are sourced manually. <Florent Kermarrec>
    |/ /
    * |   ffa7ca8f - Merge pull request timvideos#321 from gsomlo/gls-rocket-aximem-wide <enjoy-digital>
    |\ \
    | * | cd8feca5 - cpu/rocket: variants with double (128b) and quad (256b) wide mem_axi <Gabriel Somlo>
    * | |   e754c055 - Merge pull request timvideos#319 from DurandA/feature-integer-attributes <enjoy-digital>
    |\ \ \
    | |/ /
    |/| |
    | * | 94e239ff - Add integer attributes <Arnaud Durand>
    | * | f8c58216 - Revert "gen/fhdl/verilog: allow single element verilog inline attribute" <Arnaud Durand>
    * | |   40c35550 - Merge pull request timvideos#320 from gsomlo/gls-touch-up <enjoy-digital>
    |\ \ \
    | * | | 585b50b2 - soc_core: csr_alignment assertions <Gabriel Somlo>
    | * | | b6818c20 - cpu/rocket: access PLIC registers via pointer dereference <Gabriel Somlo>
    |/ / /
    * / / 0e46913d - cpu/microwatt: add initial software support <Florent Kermarrec>
    |/ /
    * | f883f0c7 - cpu/microwatt: add submodule <Florent Kermarrec>
    * | 5da0bcbd - cpu/microwatt: set csr to 0xc0000000 (IO region) <Florent Kermarrec>
    * | 39a8ebe7 - cpu/microwatt: fix add_source/add_sources <Florent Kermarrec>
    * | d74a7463 - soc/cores/pwm: remove debug print(n) <Florent Kermarrec>
    * | bd15f07c - platforms/netv2: add xc7a100t support <Florent Kermarrec>
    * | 76e57414 - platforms/minispartan6: add assert on available devices <Florent Kermarrec>
    * | bfe0bf64 - cpu/microwatt: simplify add_sources <Florent Kermarrec>
    * | b9edde20 - cpu/microwatt: add io_regions and gcc_flags <Florent Kermarrec>
    * | 16e7c6b6 - cpu/microwatt: update copyright <Florent Kermarrec>
    * | 3d79324f - cpu/microwatt: drive stall signal (no burst support) <Florent Kermarrec>
    * | da3a178b - soc/cores/pwm: add clock_domain support <Florent Kermarrec>
    * | 9da28c4e - build/xilinx/XilinxMultiRegImpl: fix n=0 case <Florent Kermarrec>
    * | ec7dc2d8 - build/xilinx/ise: cleanup/simplify pass, remove mist support (not aware of anyone using it) <Florent Kermarrec>
    * | 1b963bb2 - soc/cores/cpu: add initial Microwatt gateware support <Florent Kermarrec>
    * | c34255d2 - soc/cores/cpu/minerva: add self.reset to i_rst <Florent Kermarrec>
    * |   8b6f9e0a - Merge pull request timvideos#315 from gsomlo/gls-csr-assert <enjoy-digital>
    |\ \
    | * | a0dad1b0 - soc_core: additional CSR safety assertions <Gabriel Somlo>
    |/ /
    * | fb6b0786 - soc_core: remove static 16MB csr region allocation (use csr_address_width to allocate the correct size) <Florent Kermarrec>
    * | b1a1e5e2 - soc_core: add sort of CSR regions by origin (allow csr.h/csr.csv to be ordered by origin) <Florent Kermarrec>
    * | 061d593d - cores/8b10b: use real Memory for 6b5b table (to improve timings on ECP5) <Florent Kermarrec>
    * | a0122f98 - build/xilinx/vivado: move build_script generation <Florent Kermarrec>
    * | 18ff8f38 - build/xilinx/vivado: cleanup/simplify <Florent Kermarrec>
    * | 0931ccc9 - build/lattice/icestorm: cleanup/simplify (and remove arachne-pnr support) <Florent Kermarrec>
    * | b1b92053 - build/xilinx/common/platform/programmer: cleanup pass <Florent Kermarrec>
    * | edaa66bb - boards: add Lambdaconcept's PCIe Screamer (R02) <Florent Kermarrec>
    * | a8635c48 - targets/versa_ecp5: fix compilation with diamond <Florent Kermarrec>
    * | 30a18808 - boards/targets: keep attributes are no longer needed since automatically added when applying constraints to signals. <Florent Kermarrec>
    * | 23c33cfa - build: automatically add keep attribute to signals with timing constraints. <Florent Kermarrec>
    * | 4c9af635 - build/altera/quartus: allow adding period constraints on nets and add optional additional sdc/qsf commands <Florent Kermarrec>
    * | 22e6f5ac - build/lattice/trellis: nextpnr now handle LPF timing constraints and multiple clock domains, freq_constraint is no longer needed. <Florent Kermarrec>
    * | 8fb3f9a9 - build/lattice: cleanup/simplify (no functional changes) <Florent Kermarrec>
    * | 946478a7 - build/lattice: cleanup/simplify <Florent Kermarrec>
    * | 60edca23 - build/microsemi: cleanup/simplify (no functional change) <Florent Kermarrec>
    * | 50fdc5ce - build/altera: cleanup/simplify (no functional change) <Florent Kermarrec>
    * |   b17dfafa - Merge pull request timvideos#313 from mmicko/yosys_ise_flow_fix <Tim Ansell>
    |\ \
    | * | 783dfa50 - Properly select family for those currently supported <Miodrag Milanovic>
    | * | 6560911d - Integrate with latest yosys changes <Miodrag Milanovic>
    * | | 8d90f4e9 - build/xilinx/vivado: use VHDL 2008 as default <Florent Kermarrec>
    * | | cfd17321 - targets/nexys4ddr: remove MEMTEST_ADDR_SIZE limitation (no longer needed) <Florent Kermarrec>
    * | | 201d60f3 - targets/netv2: switch to MVP DDR3 (K4B2G1646F instead of MT41J128M16) <Florent Kermarrec>
    * | | 6b820647 - targets: uniformize, improve presentation <Florent Kermarrec>
    * | | 718f6995 - README: fix LitePCIe Travis-CI link <Florent Kermarrec>
    * | | 6de20f18 - soc/interconnect/csr: add fields support for CSRStorage's write simulation method <Florent Kermarrec>
    * | | 2567a0ae - soc/cores/gpio: add GPIO Tristate <Florent Kermarrec>
    * | | d702c0fe - setup.py: update long_description <Florent Kermarrec>
    * | | c9665aed - README.md: use litex logo <Florent Kermarrec>
    * | | 82819dd5 - README: switch to Markdown <Florent Kermarrec>
    * | |   90f9ffc5 - Merge pull request timvideos#311 from kbeckmann/trellis_cabga256 <Tim Ansell>
    |\ \ \
    | |/ /
    |/| |
    | * | f411d6d3 - trellis: Support the CABGA256 package <Konrad Beckmann>
    |/ /
    * |   3d20442f - Merge pull request timvideos#310 from xobs/spi-flash-mode3-doc <enjoy-digital>
    |\ \
    | |/
    |/|
    | * 581c2372 - spi_flash: correct documentation on SPI mode <Sean Cross>
    |/
    * de205d4a - tools/remote/comm_udp: only use one socket <Florent Kermarrec>
    * bdaca40f - build/generic_platform: avoid duplicate in GenericPlatform.sources <Florent Kermarrec>
    * 6883a436 - soc/cores/clock: change drp_locked to CSRStatus and connect it :) <Florent Kermarrec>
    * 36107cdf - soc/cores/clock: reset PLL/MMCM on all 7-series/Ultrascale with self.reset signal <Florent Kermarrec>
    *   e8e70b16 - Merge pull request timvideos#309 from antmicro/mmcm-fix <enjoy-digital>
    |\
    | * fd14b765 - soc/cores/clock: add lock reg and assign reset <Pawel Czarnecki>
    * 04017519 - soc/interconnect/axi: add Wishbone2AXILite <Florent Kermarrec>
    * 4b073a44 - test/test_axi: cosmetic <Florent Kermarrec>
    * d9055211 - build/tools/get_migen/litex_git_revision: avoid git fatal error message is not installed as a git repository <Florent Kermarrec>

 * litex-renode changed from 70e884e to 3997fff
    * 3997fff - Merge pull request timvideos#21 from antmicro/soc_controller <Tim Ansell>
    * ba983d7 - Add generation of LiteX SoC Controller <Mateusz Holenko>

 * migen changed from 0.6.dev-328-gd11565a to 0.6.dev-334-ge2e6c72
    * e2e6c72 - sayma: sata -> fat_pipe <Sebastien Bourdeauducq>
    * 7a54c79 - metlino: add ddmtd_helper_clk <Sebastien Bourdeauducq>
    * 56e1b4e - metlino: add DCXO control signals <Sebastien Bourdeauducq>
    * 084e2a2 - metlino: add clock muxes <Sebastien Bourdeauducq>
    * 4d4d055 - metlino: add SFPs <Sebastien Bourdeauducq>
    * 2480d49 - metlino: fix clk200 <Sebastien Bourdeauducq>

 * nmigen changed from f207f3f to 57d95b7
    *   57d95b7 - Merge branch 'master' of https://github.com/nmigen/nmigen <Sebastien Bourdeauducq>
    |\
    | * dfcf793 - hdl.{ast,dsl}: allow whitespace in bit patterns. <whitequark>
    * | 7245b1e - Update README. <Sebastien Bourdeauducq>
    * | 60447a0 - Merge branch 'master' of https://github.com/nmigen/nmigen <Sebastien Bourdeauducq>
    |\|
    | * a295e35 - hdl.ast: update documentation for Signal. <whitequark>
    | * 49758a3 - hdl.ast: prohibit shifts by signed value. <whitequark>
    | * cce6b86 - build.plat: align pipeline with Fragment.prepare(). <whitequark>
    | * 6fd7cba - hdl.dsl: don't allow inheriting from Module. <whitequark>
    | * afece15 - hdl.ast: warn on unused property statements (Assert, Assume, etc). <whitequark>
    | * 9fb4a4f - _unused: extract must-use logic from hdl.ir. <whitequark>
    | * 687d3a3 - hdl.dsl: add missing case width check for Enum values. <whitequark>
    | * a9da9ef - README: clarify relationship to Migen. <whitequark>
    | * 9964fc6 - hdl.dsl: make `if m.{If,Elif,Else}(...)` a syntax error. <whitequark>
    | * 3ac13eb - back.rtlil: don't emit wires for empty signals. <whitequark>
    | * b72c3fc - vendor.lattice_ecp5: support internal oscillator (OSCG). <Mike Walters>
    | * ec3a219 - build.dsl: allow strings to be used as connector numbers. <Jaro Habiger>
    | * 7792a6c - vendor.lattice_{ice40,ecp5}: Support .il (RTLIL) files in extra_files <Sylvain Munaut>
    | * c280c7c - Update README. <whitequark>
    * | c42c3a0 - vendor.lattice_{ice40,ecp5}: Support .il (RTLIL) files in extra_files <Sylvain Munaut>
    |/
    * a7be3b4 - hdl.ir: resolve hierarchy conflicts before creating missing domains. <whitequark>
    * 7cb3095 - hdl.xfrm: transform drivers as well in DomainRenamer. <whitequark>
    * e18385b - Remove everything deprecated in nmigen 0.1. <whitequark>
    * e4e2671 - Signal: allow to use integral Enum for reset value. <Staf Verhaegen>
    * 8184efd - vendor.intel: fix output enable width for XDR=0 case. <schwigi>
    * 63902dd - build.run: fix indentation. <Alain Péteut>
    * 476ce15 - back.rtlil: do not consider unreachable array elements when legalizing. <whitequark>
    * 318274d - hdl.mem: fix src_loc_at in ReadPort, WritePort. <whitequark>
    * 6765021 - hdl.ast: Fix width for unary minus operator on signed argument. <Marcin Kościelnicki>
    * 7650431 - back.pysim: fix miscompilation of Signal(unsigned) - Signal(signed). <whitequark>
    * d048f06 - hdl.ast: actually remove simulator commands. <whitequark>
    * 72cfdb0 - vendor.intel: silence meaningless warnings in nMigen files <Dan Ravensloft>
    * 7df7005 - back.pysim: redesign the simulator. <whitequark>
    * f8428ff - back.rtlil: infer bit width for instance parameters. <whitequark>
    * 56bb42a - hdl.ir: for instance ports, prioritize defs over uses. <whitequark>

Full submodule status
--
 3a6108a75be356a3dc53760d22782f1323248b6b edid-decode (heads/master)
 3a06aa84b62ad24467fb0d2c6ceddf565e9ea447 flash_proxies (heads/master)
 87578dd2e3793a25d8828a057cd888272fa4d716 litedram (remotes/origin/HEAD)
 466223e18d68da8020ab0427d90c9d6de6287de1 liteeth (heads/master)
 be68cbac60e9ff2f9c50f70bde8e4b2b2fd51683 litepcie (remotes/origin/HEAD)
 1e3573b07d382eac50ef764fd839009bf90cb8ce litesata (heads/master)
 daf10e9473fb70b3034e0331ef89005661ac04e0 litescope (heads/master)
 7457a29b1a47fe15e81fa37f3bbdd510788f1d53 liteusb (heads/master)
 146d4a73a242f6449682b58de2428cd351297c8d litevideo (heads/master)
 485934edc9c1e123e3e39911b910b51aa3196b19 litex (remotes/origin/HEAD)
 3997fffb110e00b6d4fd9d75de1f65a464ee6d89 litex-renode (heads/master)
 e2e6c726c9c34209cd326d0a80df63668285a378 migen (0.6.dev-334-ge2e6c72)
 57d95b7f95dd37e2527db7b04be9ac8f324133e2 nmigen (v0.1-38-g57d95b7)