From c357b60941c27380ad380b71542c59a9d0388e77 Mon Sep 17 00:00:00 2001 From: Mateusz Holenko Date: Wed, 9 Oct 2019 17:57:17 +0200 Subject: [PATCH] Updating submodules. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit * edid-decode changed from 42f5fa4 to 7d26052 * 7d26052 - edid-decode: improve "Invalid Detailed Timings" message * 0da30bd - edid-decode: Avoid division by zero * ea15b91 - edid-decode: add ELO 4600L EDID * 7696439 - Add LG 32UD99-W edid from the DP (USB-C) input * 0932dee - Add LG 32UD99-W edid from the HDMI input * 3bd8bbe - Add EDID for LG OLED55E6V * d5fb521 - Add an EDID for the Samsung UE48JU7090 * flash_proxies changed from 1c21ee4 to 01d8f81 * 01d8f81 - remove bscan_spi_xcku040-sayma * litedram changed from 6c53996 to 5d1a984 * 5d1a984 - core: add LiteDRAMCore (ControllerInjector from LiteX) * d647abd - gen: fix with_wishbone * db97203 - gen: use SoCCore with_wishbone parameter, do more replace in yml files before passing config to LiteDRAMCore * adf481f - gen: disable peripherals that are not used when cpu_type is None * 2331919 - gen: change CSR config names, switch to csr_expose/csr_align * da408a3 - gen: fix default csr_port_align value * bac66aa - gen: In conjunction with the corresponding changes in litex itself, this will allow us to generate a more useful standalone litedram core. * afbf709 - We had the address and data bus sizes mixed up * d93dded - frontend/wishbone: add data_width assertions * f586aad - phys: improve presentation (add separators, better indent) * 783258c - phys: use dfi instead if self.dfi internally * 59c1289 - phy/usddrphy: move DDR4DFIMux to dfi.py * f861d99 - core/refresher: improve naming/parameters of refresh postponing * dc1bb53 - phys: move get_cl_cw/get_sys_latency/get_sys_phases helpers to common * 509f606 - README: add periodic refresh/ZQ short calibration. * 40b4c62 - test/test_init: fix * 5b48eb2 - test/test_init: delete generated file * 188b6a8 - add ZQ periodic short calibration support (default to 1s) * 6e176d4 - init: split by memtype * 0b24b81 - test: add test_init with sdr/ddr3/ddr4 references * bf5883c - rename sdram_init to init * 23ccdc9 - modules: add DDR3 MT8KTF51264 SO-DIMM * d37a30e - litedram_gen: add wishbone user port support * b6a0eff - frontend/wishbone: split control/data paths (to avoid data muxes) * 6497343 - frontend/wishbone: remove IDLE fsm state * 00ecb87 - gen: add separators * a782eb5 - test/test_examples: adapt for travis * f678efa - travis: add pyyaml * 8861d80 - Merge pull request #91 from sd-fritze/master |\ | * fe2cc94 - modules: Add support for Micron MT47H32M16 DDR2 RAM |/ * a23b9e7 - core/refresher: set cmd.valid to 0 when sequencer done * 12ddc13 - litedram/gen: add description and switch to argparse * 2bdeda0 - move standalone core generation to litedram package and make it usable externally * 0dde125 - examples/litedram_gen: fix #!/usr/bin/env python3 location * 602ff8b - examples: switch to YAML config files * fb28f79 - core/refresher: remove load/load_count on RefreshTimer (not used) * 1c69f49 - core/controller: allow user provided Refresher * b64daba - core/controller: add separators, ease readibility * 338d18d - core/refresher: add capability to accumulate N refreshs and execute the N refreshs together * 818c4ca - core/refresher: another cleanup pass * 80c8ecf - core/multiplexer: rewrite arbiter comment * 37db416 - core/refresher: another cleanup pass * f0592ff - core/refresher: add comments * de38b52 - core/refresher: rename RefreshGenerator to RefreshSequencer and simplify * 8573c22 - phy/gensdrphy: add assertions on length of pads.dq/pads.dq * liteeth changed from ad187d3 to 4d9e74f * 4d9e74f - phy/usrgmii: cleanup (style, indent) * 4bc79ce - examples/targets/core: update * cd0eaa9 - Merge pull request #19 from jersey99/master * 59e0460 - Adds RGMII phy support for Xilinx Ultrascale Devices. Hardware tested on HTG-940 * litepcie changed from 71c9a3a to 47e76f4 * 47e76f4 - example/dma: keep up to date with litex * 7f9367c - example/make: keep up to date with litex * c6a536a - frontend/dma: add optional underflows/overflows monitoring, rename tx_fifo/rx_fifo to reader_fifo/writer_fifo * 6bb4a60 - frontend/dma/buffering: expose fifo levels to CSRs * litescope changed from 9e3b9d8 to 7a9fa9d * 7a9fa9d - core: use new CSRStatus.we signal to speed-up Storage upload (>10x speedup over ethernet) * 284253d - core: add csr_csv parameter and export csv_csv on do_exit * 69a8df0 - Merge pull request #14 from DurandA/master * 06cac3a - Use cpu instead of cpu_or_bridge in examples * litevideo changed from 98e145f to 49bafa4 * 49bafa4 - input/dma: no longer use aligment_bits of CSRStorage * litex changed from e637aa65 to b627a8fe * b627a8fe - cpu: add default io_regions to CPUNone (all address range can be used as IO) * cc245fc8 - Merge pull request #275 from pcotret/patch-1 |\ | * e923a88d - Update README (related to issue #273) * | a6b3aa3c - soc_core: improve check_io_region error message * | dc656d48 - targets/sim: switch from shadow_base to io_regions * | 10146abf - cpu/rocket: move csr to IO region * | 7f1d4623 - build/xilinx/vivado: fix default synth-mode * | a4ef9b29 - soc_core/cpu: add io_regions and deprecate shadow_base (with API retro-compat) |/ * e8b90e80 - Merge pull request #274 from gsomlo/gls-shadow-base |\ | * 53777391 - builder: use the SoC's existing shadow base with get_csr_header() |/ * 92975b13 - targets/arty: allow setting synth-mode to yosys with command line: --synth-mode=yosys * 4a1cefe9 - build/xilinx/vivado: add vivado_build_args/vivado_build_argdict for yosys synthesis mode * 3e22d4b9 - xilinx/common: be sure language is not vhdl when yosys synthesis is used * 975bd9be - cpu/vexriscv: use specific mem_map for linux variant * 2dfe7441 - Merge pull request #271 from gsomlo/gls-yosys-nowidelut |\ | * 6aa76b1d - trellis, versa_ecp5: optional '-nowidelut' flag for yosys synth_ecp5 * | c954ff0c - Merge pull request #272 from sergachev/fix-comments |\ \ | |/ |/| | * 2f7bd971 - fix comments * | ab4a5d1d - litex_setup: add litejesd204b |/ * 960b25a5 - Merge pull request #270 from gsomlo/gls-csr-upper |\ | * c8790d34 - soc/integration: ensure CSR constants are in uppercase * | 41ad08e8 - soc/cores/icap: simplify ICAPBitstream (untested) * | 0c299386 - soc/cores/icap: rename ICAP to ICAPBistream and revert old ICAP * | 4bb2827e - Merge pull request #269 from antmicro/rework_icap |\ \ | |/ |/| | * 4423a46b - soc: cores: support sending custom bitstream to ICAP * | 427d7af7 - soc/interconnect: rename stream_packet to packet & cleanup (with retro-compat) * | 59bf04d9 - soc/interconnect/stream: add separators, mode Actor modules just after Endpoint * | 59995c53 - soc_zynq: update get_csr_header * | 4d90058b - soc/integration: move cpu_interface retro-compatibility to litex/__init__ * | 8be5824e - soc/integration: use dicts for constants/mem_regions/csr_regions to cleanup/simplify iterations on theses * | 7b72148c - cpu: remove initial SERV support (we'll work in a branch to experiment with it) * | 63a813af - soc_core: fix cpu_type=None case and add test for it * | 3d257d72 - soc_sdram: remove axi usecase, this was only useful to do some preliminary axi tests. * | e8e57b4f - soc_core: cleanup/re-align * | 334ae336 - soc/integration: rename cpu_interface to export (with retro-compat), re-arrange a bit, add separators * | 241c3c64 - test/test_targets: update cpu-type to mor1kx * | 48e5a1d1 - soc/cores: uniformize (continue) * | e9ed4761 - soc/cores/gpio: uniformize with others cores * | 78cecbe3 - soc/cores: rename frequency_meter to freqmeter and uniformize with others cores * | 7575ecc6 - soc/cores/ecc: improve readibility, uniformize with others cores * | c6fe3f31 - soc/cores/clocks: improve readibility * | 6fcb12a9 - soc_core: use cpu.data_width to compute csr_alignment (and remove Rocket workaround) * | b826c170 - soc/cores/cpus: improve ident/align, uniformize between cpus * | 355072c2 - soc/cores/cpu: add CPU class and make all CPU inheritate from it * | 2c3ad3f9 - soc_sdram: move ControllerInjector to LiteDRAM (LiteDRAMCore) * | 101f1b1c - soc/integration: add common.py and move helpers from soc_core to it * | 68ba1c60 - soc_core: avoid manual listing of support CPUs, just use CPU.keys() * | 9095b80e - soc_core: remove add_cpu_or_bridge retro-compatibility (most of the designs have been updated since the change) * | 8dd2dc1c - integration/soc_core: remove csr_map_update (no longer used) * | da91aa43 - soc_core/cpu: move memory map override to CPUs, select reset_address after eventual memory map has override been done * | 8099b0be - soc/cores/cpu: add set_reset_address method and use it instead of passing reset_address as a parameter * | 7660dc22 - soc/cores/cpu: do instance in do_finalize for all cpus (allow updating parameters until the design is generated) * | a3816096 - cores/cpu: define CPUS and simplify instance * | 9f6a2ae7 - soc_core/serv: use UART_POLLING (no interrupt support) * | a4069fc8 - add SERV submodule * | 49594ed7 - software/libbase/uart: add polling mode * | 3f95b9c0 - add SERV CPU initial support (not working) * | 015b65fe - targets/ulx3s: revert to cl=2 * | a9d55b04 - boards/netv2: switch to MVP, add spiflashx4 and hdmi in/out * | 1425a68d - wishbone2csr: refactor using FSM, reduce latency (make it asynchronous) and set csr.adr only when access is done (allow use of CSR/CSRBase we signal) * | ffd2be2b - csr: add we signal to CSR, CSRStatus * | 47dc3324 - build/xilinx/programmer: fix vivado_cmd * | ed9bff2e - soc/integration/doc: replace "== None" by "is None" * | 836d5b88 - Merge pull request #266 from xobs/add-moduledoc-autodoc |\ \ | * | 68cea8c3 - timer: inherit ModuleDoc | * | 13197198 - integration: add ModuleDoc and AutoDoc * | | 78fb0fb9 - tools/litex_read_verilog: also delete yosys_v2j.ys * | | 0ea7a1fd - soc_core/sdram: Don't blow up if _wb_sdram_ifs or _csr_masters are empty * | | 742da31b - Merge pull request #264 from antmicro/mor1kx_linux |\ \ \ | * | | 5844376d - soc_core: adapt memory map for mainline Linux with mor1kx | * | | 201218b2 - boards/targets: increase integrated ROM size if EthernetSoC is used * | | | 06d08064 - soc_core: set csr to 0x00000000 when there is no wishbone * | | | ad8830d9 - soc_sdram: Don't add the L2 Cache when there's no wishbone bus |/ / / * | | ae38fd42 - soc_core: revert wishbone2csr to __init__ but add with_wishbone parameter * | | 8c979565 - soc_sdram: change l2_size checks order * | | a9acab99 - soc_core: move CSR bridge to finalize (only generate it if there is a wishbone master), revert default parameter when cpu_type is None (we have systems with cpu_type=None but that are using these peripherals) * | | dde6dd02 - integration/builder: avoid specific _generate_standalone_includes * | | 735ea196 - This will allow it to be built for microwatt out of tree * | | c28086cd - soc_core: When cpu_type is "None", let's not generate useless UART, timer, ROMs, wishbone to CSR bridge etc... * | | f909e4d7 - integration/builder: When the CPU is "None", we used to not generate any code. |/ / * | 8b7d8217 - Merge pull request #263 from xobs/spi-flash-csrfield |\ \ | * | 1a6dddd5 - spi_flash: document register fields |/ / * | 4f659ba4 - Merge pull request #262 from jersey99/master |\ \ | * | 9ea11cf5 - vivado just needs to be in the path for the programmer as well |/ / * | 430fee4d - Merge pull request #261 from xobs/event-documentation |\ \ | |/ |/| | * 60d8572c - csr_eventmanager: add `name` and `description` args |/ * e2c78572 - cores/timer: add general documentation on Timer implementation and behavior. * e97c1e36 - soc_sdram: improve readibility and convert l2_size to minimal allowed if provided l2_size is lower * 99ed0877 - csr: add description to CSRStorage/CSRStatus attributes (thanks xobs) * f2e84a58 - soc/cores/timer: fix typo (thanks xobs) * 28885064 - soc/cores/timer/doc: rewrite a little bit, avoid some redundancy, change ident. * f1139c36 - Merge pull request #259 from xobs/document-timer |\ | * cb7d941a - timer: add documentation |/ * cca0478a - soc/cores/spi: use new CSRField (no functional change) * 80b2bef3 - soc/cores/bitbang: use new CSRField (no functional change) * 3dc8d294 - Merge pull request #257 from enjoy-digital/csr_fields |\ | * 9bda614a - csr: update copyrights | * 29134cc6 - csr: more documentation | * 74e756aa - csr/CSRStorage: remove storage_full (was only needed by alignment_bits) | * 5dc440e8 - csr: use IntEnum for CSRAccess | * d2646f13 - csr/CSRStorage: remove alignment_bits: complexify too much code for the few use-cases it's really useful | * 8e14694e - csr/fields: document, add separators, 100 characters per line | * 4e84729c - csr/fields: add access parameter | * 23b01f8f - csr/fields: add pulse mode support | * 8c080e5f - soc/interconnect/csr: add initial field support |/ * c120f6d4 - build/openocd: add set_qe parameter to flash * 6a0a1c9d - tools/litex_term/upload: bufferize only chunks of the file instead of the entire file to speedup upload when used on embedded devices (RPI for example) * 16b6b357 - soc/integration/cpu_interface: don't raise OSError if we are not going to compile software and compilation toolchain is not found * 62f53d50 - soc/integration/builder: call do_exit with vns when build is done. * cb5f1467 - Merge branch 'master' of http://github.com/enjoy-digital/litex |\ | * a7b5c185 - Merge pull request #255 from sergachev/fix-crc32 | |\ | | * 2400f0f4 - fix crc32 | |/ * | 004c96b5 - soc/itnegration: update litedram |/ * 19f58dd9 - interconnect/wishbone: add FlipFlop to allow UpConverter to be used * bd6ec63b - build/openocd: add stream method for JTAG UART * b356204f - soc_core: add JTAG UART support (uart_name="jtag_uart) * d0ebbda4 - soc/cores/jtag: add Xilinx JTAG TAPs support and simple JTAG PHY (can be used for JTAG UART) * 2638393b - soc_zynq: fix indent * 9051cf97 - soc_zynq: fix typo * 67a09aef - soc/interconnect/stream: add Monitor module * 6f150a56 - Merge pull request #254 from mithro/crc-smaller |\ | * 2a41f0d2 - Use `SMALL_CRC` to enable smaller CRC versions. | * 08333744 - Remove extra whitespace. | * c0e72386 - libbase: crc16: commit smaller version of crc16 | * a59d0efc - libbase: crc32: add smaller version * | 27c334d4 - Merge pull request #252 from mithro/only-change-on-contents |\ \ | |/ |/| | * 3ff6a18a - Only write file if contents will change. |/ * a2938a7a - soc/cores: simplify JTAGAtlantic (only keep alt_jtag_atlantic instance), move to jtag and allow selecting it as uart with uart_name"jtag_atlantic" * 19d3acfc - Merge pull request #251 from micro-FPGA/master |\ | * fb00ee85 - Create atlantic.py | * 92e5b4b2 - Merge pull request #2 from enjoy-digital/master | |\ | * | f47e4978 - libero enable enhanced constraints * | | 41fe7cae - core/spi: add minimal SPISlave * | | b8457559 - gen/fhdl/verilog: allow single element verilog inline attribute * | | 5a7b4c34 - targets/nexys_video: generate clk100 * | | c179741c - software/bios: switch to standard CRLF * | | 0328ba7d - tools/litex_term: add automatic check to see if we need to insert LF or not * | | ffebd207 - bios/tools: allow disabling CRC check on serialboot (to speedup debug/loading large images when only serial is available) * | | 4842bdcf - tools/litex_term: add sdl_payload_length * | | 3e30c648 - litex_setup: add litex-boards * | | d79cd87d - Merge pull request #246 from gsomlo/gls-native-rv64 |\ \ \ | * | | 6d844a03 - software: use native toolchain for same host, target architectures |/ / / * | | d36f1fb7 - Merge pull request #244 from atommann/master |\ \ \ | |_|/ |/| | | * | a45dbee5 - changing http to https | * | 1d957d7a - Update .gitmodules * | | 4990bf33 - soc/core: simplify/cleanup HyperRAM core - rename core to hyperbus. - change layout (cs_n with variable length instead of cs0_n, cs1_n). - use DifferentialOutput when differential clock is used. - add test (python3 -m unittest test.test_hyperbus). * | | d1502d41 - soc/cores: add initial simple hyperram core | |/ |/| * | 6e6fe83a - build/altera/quartus: add add_ip method to use Quartus QSYS files * | 2899928a - cpu_interface: add json csr map export, simplify csv csr map export using json * | 9d4b7cd5 - bios/sdram: set init done after memtest (for standalone LiteDRAM controllers) * | 0cd4e45f - build/xilinx/vivado: use "" for strings * | 8d161a47 - build/xilinx/vivado: remove with_phys_opt * | f6638ded - Merge pull request #243 from sergachev/master |\ \ | * | 861eea8a - build/xilinx/vivado: improve directive support * | | ccc2cbd9 - Merge pull request #241 from railnova/zynq |\ \ \ | |/ / |/| | | * | db4c609a - [fix] prevent Vivado from inferring DSP48 in AXIBurst2Beat |/ / * | 6d5fddc1 - cores/spi_flash/S7SPIFlash: make cs_n optional in pads (when driven externally) * | 383c05e2 - Merge pull request #240 from danielkucera/patch-1 |\ \ | |/ |/| | * a5eaf172 - more understandable error when missing a memory |/ * 2b815f70 - Merge pull request #235 from gsomlo/gls-trellis-yosys-opt |\ | * 6c298cb7 - build/lattice/trellis: use abc9 techmapping pass with yosys |/ * 31bfb546 - software/libbase/mdio: set data before clock, revert two cycle turnaround and test with different phys * e670cb91 - cores/cpu: add riscv-none-embed toolchain support to riscv32 cpus * 6d94c07d - software/libase/mdio: cleanup and reduce raw_turnaround by 1 cycle * 0c287b11 - cores/clock/S7PLL: fix -1/-3 speedgrade vco max freq swap * 82cd557c - software/bios: add Ethernet PHY MDIO read/write/dump commands * 0ba9ab92 - altera/common: fix AsyncResetSynchronizer polarity and simplify * 124dff8f - build/xilinx/common: improve presentation * 60873a5b - microsemi/common: improve presentation * 36d9d78c - build/altera/common: improve presentation * 95953d29 - platforms/default_clk_period: use 1e9/freq * f1d8c70b - targets/minispartan6/crg: only keep S6PLL code * d3d0a623 - cores/clock: juse use 1e9/freq instead of period_ns * a881817f - cores/clock/s6pll: add phase support * 6b7ca0cf - cores/clock/xilinx: change clkfbout_mult loop order to select highest vco_freq * 1884649d - litex_term: make sure to unconfigure console when board is unplugged * e052d7f6 - soc/integration/builder: -x * 236070fd - cores: -x on spi.py * a9fe2788 - wishbone/SRAM: make read_only emited verilog code compatible with all tools * ce5c5859 - soc/cores/uart: add FT245 FIFO mode support (sync & async) * a496760c - build/altera/quartus: use .bat on win32/cygwin * 7e0ea070 - build/xilinx/vivado: change severity of Common 17-55 critical warning to warning * 92d93ad2 - cores/pwm: remove default CSR reset values. * 25ca0a8b - soc: generate git header and show migen/litex git sha1 in bios * ae00482d - Merge pull request #223 from sergachev/master * fdb119cb - support vivado incremental implementation * litex-renode changed from a57aa47 to b3fdb9b * b3fdb9b - Merge pull request #13 from antmicro/xip_flash |\ | * 2080118 - Generate LiteX SPI Flash with underlying memory |/ * e4ebebf - generate-renode-scripts: be sure kind/variant are in uppercase * 4c072c8 - litex directory: add missing __init__.py * dcd3fd8 - Extract HDMI2USB mocserver code to a separate file * 2bb663f - Extract LiteX configuration parser * e3c51a4 - Make this repo a proper python package * 30d044e - Merge pull request #11 from CarlFK/master |\ | * e2f6a00 - adds --json-file and code to create a json file for the moc server. | * b581fd6 - make a main() and parse_args() * | eaeae9b - Merge pull request #12 from antmicro/rename_litex_spi_flash |\ \ | |/ |/| | * 401babc - Adapt to LiteX_SPI model rename |/ * 301b0fd - Merge pull request #10 from antmicro/fix_gdb |\ | * 8a3a55b - Adapt to GDB API changes in Renode * 3a4943c - Merge pull request #9 from antmicro/6-improve_readme * cccefd4 - [#6] Improve the README. * migen changed from 0.6.dev-289-g5585912 to 0.6.dev-306-g41922fd * 41922fd - sayma_amc2: amc_fpga_sysref* * 3714470 - sayma_amc: fix dac_sync pin locations * 4a6ef29 - sayma_amc2: DAC JESD links have been swapped * 3012df6 - sayma_amc2: sma_io -> mcx_io * ecf8412 - sayma2: remove serwb * fc31a9e - sayma_rtm2: add HMC workaround signals * 21b2fbd - sayma_rtm2: fix swapped scl/sda * 0114468 - sayma_rtm2: cross UART * 5a28590 - sayma_rtm2: clk50 is DNP, use GTP clock instead * ef7dab2 - sayma_rtm2: always xc7a50t * 63a5f55 - sayma_rtm2: add filtered_clk_sel signal * 9211304 - sayma_amc2: add filtered_clk_sel signal * 9e59e41 - sayma_amc2: fix typo in previous commit * 58d9c82 - sayma_amc2: fix ddram_32 assignments * 57a7311 - Added support for the Xilinx AC701 FPGA development board * f4fcd10 - fix previous commit * 34f24f3 - zedboard: use Vivado toolchain Full submodule status -- 7d26052f7245664df96079845601ced5335fb2d7 edid-decode (remotes/origin/HEAD) 01d8f819f15baf9a8cc5d96945a51e4d267ff564 flash_proxies (remotes/origin/HEAD) 5d1a9847aa805034e58eabf376e2807bfed7b133 litedram (remotes/origin/HEAD) 4d9e74f10a3fe7bf71ba9bde50f49689c6458dc5 liteeth (remotes/origin/HEAD) 47e76f447f6e3d97aac2638a98f967d44db5c349 litepcie (remotes/origin/HEAD) db5d2f7881161ce5b9a10a0ab42555f884b9d7c1 litesata (heads/master) 7a9fa9d3b18362bf707dff25a78661395ef9ee7a litescope (remotes/origin/HEAD) 7457a29b1a47fe15e81fa37f3bbdd510788f1d53 liteusb (heads/master) 49bafa481075e0bfbaf067b63c351ec29e993894 litevideo (remotes/origin/HEAD) b627a8fe71b55f1987a9cd5181da14cddd3203c1 litex (remotes/origin/HEAD) b3fdb9ba5ebc22b214fbd78fa4f2eeb1ac393805 litex-renode (remotes/origin/HEAD) 41922fde2a8c36cd0f99d4b7ebb3ba9c37ce1489 migen (0.6.dev-306-g41922fd) --- third_party/edid-decode | 2 +- third_party/flash_proxies | 2 +- third_party/litedram | 2 +- third_party/liteeth | 2 +- third_party/litepcie | 2 +- third_party/litescope | 2 +- third_party/litevideo | 2 +- third_party/litex | 2 +- third_party/litex-renode | 2 +- third_party/migen | 2 +- 10 files changed, 10 insertions(+), 10 deletions(-) diff --git a/third_party/edid-decode b/third_party/edid-decode index 42f5fa4ed..7d26052f7 160000 --- a/third_party/edid-decode +++ b/third_party/edid-decode @@ -1 +1 @@ -Subproject commit 42f5fa4ed99b669da4b4169a42eca7dbf5a293c7 +Subproject commit 7d26052f7245664df96079845601ced5335fb2d7 diff --git a/third_party/flash_proxies b/third_party/flash_proxies index 1c21ee44a..01d8f819f 160000 --- a/third_party/flash_proxies +++ b/third_party/flash_proxies @@ -1 +1 @@ -Subproject commit 1c21ee44a2b3936f62e4b43f2bcbf63ce9404691 +Subproject commit 01d8f819f15baf9a8cc5d96945a51e4d267ff564 diff --git a/third_party/litedram b/third_party/litedram index 6c53996a7..5d1a9847a 160000 --- a/third_party/litedram +++ b/third_party/litedram @@ -1 +1 @@ -Subproject commit 6c53996a7042050def908882b36e92585b6ef138 +Subproject commit 5d1a9847aa805034e58eabf376e2807bfed7b133 diff --git a/third_party/liteeth b/third_party/liteeth index ad187d35f..4d9e74f10 160000 --- a/third_party/liteeth +++ b/third_party/liteeth @@ -1 +1 @@ -Subproject commit ad187d35f2b967eb152adcc9f1998a914e5bb53a +Subproject commit 4d9e74f10a3fe7bf71ba9bde50f49689c6458dc5 diff --git a/third_party/litepcie b/third_party/litepcie index 71c9a3a2e..47e76f447 160000 --- a/third_party/litepcie +++ b/third_party/litepcie @@ -1 +1 @@ -Subproject commit 71c9a3a2eeaae8c4c44ffae14fb5417b94319206 +Subproject commit 47e76f447f6e3d97aac2638a98f967d44db5c349 diff --git a/third_party/litescope b/third_party/litescope index 9e3b9d84c..7a9fa9d3b 160000 --- a/third_party/litescope +++ b/third_party/litescope @@ -1 +1 @@ -Subproject commit 9e3b9d84ce6d0e895d0ac275df78ccbd0e0e0ab2 +Subproject commit 7a9fa9d3b18362bf707dff25a78661395ef9ee7a diff --git a/third_party/litevideo b/third_party/litevideo index 98e145fba..49bafa481 160000 --- a/third_party/litevideo +++ b/third_party/litevideo @@ -1 +1 @@ -Subproject commit 98e145fba8c25394e9958bad67e2a457d145127e +Subproject commit 49bafa481075e0bfbaf067b63c351ec29e993894 diff --git a/third_party/litex b/third_party/litex index e637aa657..b627a8fe7 160000 --- a/third_party/litex +++ b/third_party/litex @@ -1 +1 @@ -Subproject commit e637aa657b7c1163c7c21c4b972f4aa947406272 +Subproject commit b627a8fe71b55f1987a9cd5181da14cddd3203c1 diff --git a/third_party/litex-renode b/third_party/litex-renode index a57aa47ff..b3fdb9ba5 160000 --- a/third_party/litex-renode +++ b/third_party/litex-renode @@ -1 +1 @@ -Subproject commit a57aa47ff6863f08d75d33fb5545ea489817ac0d +Subproject commit b3fdb9ba5ebc22b214fbd78fa4f2eeb1ac393805 diff --git a/third_party/migen b/third_party/migen index 558591288..41922fde2 160000 --- a/third_party/migen +++ b/third_party/migen @@ -1 +1 @@ -Subproject commit 558591288dd08302cb8830310ba6975757b58c72 +Subproject commit 41922fde2a8c36cd0f99d4b7ebb3ba9c37ce1489