From ddc5f3ae7818d5b1abd6c082fc90b44ec05da13e Mon Sep 17 00:00:00 2001 From: Mateusz Holenko Date: Tue, 25 Aug 2020 14:11:59 +0200 Subject: [PATCH] Updating submodules. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit * litedram changed from f51052f to 2020.08-3-g5c69da5 * 5c69da5 - bench: add initial kcu105 bench target. * 9995c0f - bench: switch integrated_rom to "rw" mode and reload it over Etherbone at startup. * ac825e5 - add SPDX License identifier to header and specify file is part of LiteDRAM. * 198bcba - test/reference: update. * e3b86fe - getting started: update. * a0a886e - litedram/init: export xdr ratio and databits. * 94241d0 - bench: use new platform.request_all on LedChaser. * 7420597 - bench: add genesys2 bench. * 37fb44f - add bench directory with a first bench on arty board. * 4e62d28 - examples/.yml: set cmd_latency to 1 on Kintex7/Ultrascale (values valided in LiteX-Boards). * 07bf34d - frontend/wishbone: revert non-FSM version, the FSM one does not seem to cover all cases. * 9c5ce52 - common: add connect method to LiteDRAMNativePort and use it in adapter for identify converter. * 06f7192 - frontend/adapter/LiteDRAMNativePortConverter: simplify using ratio. * a3dfc1d - frontend/adapter: minor cleanups. * deac4c8 - frontend/adapter: simplify LiteDRAMNativePortDownConverter. * ce4e7f9 - frontend/adapter: simplify LiteDRAMNativePortCDC using stream.ClockDomainCrossing. * 16fd46b - frontend: rename adaptation to adapter. * 4970c8a - frontend/wishbone: simplify/review and get FSM back (ease comprehension). * 47a0d5f - litedram_gen/LiteDRAMUSDDRPHYCRG: remove AsyncResetSynchronizer on sys/sys4x (reset handled by USIDELAYCTRL). * 02e67ec - Merge pull request #192 from antmicro/jboc/port-adaptation |\ | * 22bd01c - frontend/wishbone: simplify by reusing LiteDRAMNativePortConverter | * b0bde29 - frontend/wishbone: fix wb2native missing wdata.ready when wb/port data widths differ | * 79314f9 - frontend/wishbone: fix wdata.valid being high with old data, use cmd.last=1 | * 000a352 - frontend/adaptation: delay sending write commands to prevent data loss during up-conversion | * 84fb7d3 - frontend/adaptation: refactor up-converter logic to use FSM for clarity | * efe9a44 - frontend/adaptation: clean up LiteDRAMNativePortUpConverter code | * 2f35e97 - frontend/adaptation: fix error when read follows write to the same address | * 1587ee3 - frontend/adaptation: use port.cmd.last instead of port.flush in up-converter | * 35fa91c - test/crossbar: up-conversion with mode="both" should be working now | * 9b90a56 - frontend/adaptation: combine read/write port up-converters and extend tests | * 762cd6d - test/adaptation: add port converter tests with mode="both" | * 7a0f7a7 - test/common: fix error in test data | * 1cc9656 - test/crossbar: improve NativePortDriver to use separate generatos on data paths | * 025e280 - test/crossbar: fix test that was not being run * 71b991e - Merge pull request #210 from oskirby/ddr3-tdqs-mode |\ | * 805a374 - Add support for TDQS mode. |/ * c01e868 - phy/gensdrphy/HalfRateGENSDRPHY: review/simplify and reduce read_latency by 1. * liteeth changed from 792013a to 54acf9f * 54acf9f - phy/pcs_1000basex: keep up to date with MiSoC (adds SGMII and 10/100Mbps support). * 64b85e6 - add SPDX License identifier to header and specify file is part or LiteEth. * f275af8 - liteeth_gen: get Wishbone Platform's IOs with Interface.get_ios. * 0705b35 - Merge pull request #46 from Xiretza/gen-py-wishbone * 6a9a513 - Update gen.py to work with latest LiteX in wishbone mode * liteiclink changed from 6fdd020 to 2020.08-1-gefd200f * efd200f - add SPDX License identifier to header and specify file is part of LiteICLink. * 60b1994 - getting started: update. * litepcie changed from 0b6a4bb to 2020.08-1-g0718fd1 * 0718fd1 - add SPDX License identifier to header and specify file is part of LitePCIe. * 29d4963 - getting started: update. * 30456fc - litepcie_gen: add csr_ordering support. * litesata changed from b36d3a3 to 2020.08-1-gba006a7 * ba006a7 - add SPDX License identifier to header and specify file is part of LiteSATA. * 2e4591c - getting started: update. * litescope changed from 15179cb to 2020.08-2-g02b543e * 02b543e - litescope_cli: add capture subsampling support. * 2739d5a - add SPDX License identifier to header and specify file is part of LiteScope. * ec7bd6b - getting started: update. * 7d22774 - Merge pull request #27 from cklarhorst/fix-storage-wrong-clock-domain |\ | * ad4e46c - Fix: 2 signals in the storage class belong to the wrong clock domain |/ * 2ad73a0 - Merge pull request #25 from cklarhorst/fix-trigger-flush-timer-wrong-clock-domain |\ | * 16e6555 - Fix: A WaitTimer belongs to the wrong clock domain (trigger flush) |/ * 0066866 - travis: install riscv toolchain for example. * 6a322ed - test/test_examples: update. * bc6c5e3 - examples: add mininal example on Arty with Etherbone and ibus/counter on analyzer. * 0182377 - examples: remove obsolete examples rename litescope_test to litescope_cli and add it as console script. * a80c964 - Merge pull request #22 from antmicro/jboc/test-script * 8b0274d - examples: add a more general script for testing * litex changed from 9fc488bd to 3897acb9 * 3897acb9 - lattice/nx: update copyrights. * 4364043b - integration/soc: expose integrated_rom_mode to allow ROM to be writable (useful for BIOS/ROM development where content is reloaded over UARTBone/Etherbone). * 885c339d - soc/cores: add initial NX-LRAM support. * cf13833e - cores/clock: add initial NX-OSCA support. * e441bd60 - build/lattice: add initial Radiant support for NX FPGA family (Crosslink-NX/Certus-NX). * 8a44464a - Merge pull request #640 from antmicro/mor1kx_dt |\ | * 4dab1eb0 - litex_json2dts: Add support for mor1kx * | 4f1c32ab - targets/de0nano: set sys2x_ps to 180° for sdram_rate=1:2. * | d16051ff - boards/ulx3s: keep up to date with litex-boards. * | d826c606 - soc/cores/clock/ECP5PLL: specificy CLKOS3_F/CPHASE and -1 on cphase to match Clarity Designer values. * | 9e37b16e - soc/interconnect/axi/AXILite2CSR: add register parameter for genericity. |/ * 42d8fc22 - Merge branch 'master' of https://github.com/enjoy-digital/litex |\ | * ee0e2402 - Merge pull request #631 from gsomlo/gls-abc9-fixup | |\ | | * c4710b37 - build/lattice/trellis: make "-abc9" an optional argument * | | 77ae2433 - test: add SPDX License identifier to header and specify file is part of LiteX. * | | b8371ef4 - tools: add SPDX License identifier to header and specify file is part of LiteX. * | | 93d906f9 - soc: add SPDX License identifier and specify file is part of LiteX. * | | e52ffd2d - gen: add specify SPDX License identifier and specify file is part of Migen and has been modified/adapted for LiteX. * | | 70610b23 - build: add SPDX License identifier and specify file is part of LiteX. * | | 6ee882d1 - platforms/targets: add SPDX License identifier to header and specify file is part of LiteX. |/ / * | 9950e756 - build/io: fix InferedSDRIO (thanks @mtdudek). * | bae871a8 - Merge pull request #632 from gsomlo/gls-sdcard-refactor |\ \ | * | e0b2b815 - liblitesdcard/sdcard: read sdcard response only when needed | * | a47b2de5 - sdcard: refactor command functions | * | bfd6b3c3 - liblitesdcard/sdcard: cosmetic fixes (indentation, #ifdef, etc.) | * | 37ebcd3b - factor out busy_wait_us() | |/ * | 3206dba9 - Merge pull request #636 from Xiretza/minerva-cli-filetype |\ \ | * | e3bb3a94 - Fix call to generation of minerva output file | |/ * | 8bc5dd7c - Merge pull request #635 from Xiretza/collections-abc-deprecation |\ \ | * | fcc7058b - Fix DeprecationWarning for collections.abc | |/ * | 79844362 - Merge pull request #634 from betrusted-io/spi_opi_timing_only |\ \ | |/ |/| | * d783e86f - add a pipe register to relax an async_default timing path * | 35929c0f - soc/integration/csr_bridge: use registered version only when SDRAM is present. * | e4f5dd98 - interconnect/wishbone/Wishbone2CSR: add registered version and use it as default. * | b344196a - build/lattice/diamond: use diamondc instead of pnmainc (avoid having to set environment variables). * | f730f1d7 - cores/cpu/vexriscv_smp fix argument parsing * | 0e480dd6 - bios/main/sdram: fix speed reporting (Mbps/pin not MHz). * | bb7f3343 - Merge pull request #627 from gsomlo/gls-dma-addr-64 |\ \ | * | ba34c852 - cores/dma, liblitesdcard/sdcard: use 64 bits for dma base address |/ / * | 4cf28a01 - software/bios: display SDRAM databits and freq. * | 6f69679d - cpu/vexriscv_smp: more coherent_dma to __init__ instead of add_memory_buses. * | b3531cd2 - cores/cpu: add external cpu_type. * | b9d3aab5 - targets: use platform.request_all on LedChaser. * | 14c91664 - build/generic_platform: add request_all method. * | 57335b99 - cores/cpu/zynq7000: simplify using new loose parameter of Platform.request. * | 4867f2b3 - Merge pull request #624 from trabucayre/emio_zynq |\ \ | * | 87c26a30 - soc/cores/cpu/zynq7000: add enet0, enet0_mdio, sdio, sdio_cd and sdio_wp only when configured in EMIO mode * | | 48d63f23 - build/generic_plaform: add loose parameter to return None when not available/existing. * | | 81df7b70 - Merge pull request #625 from scanakci/blackparrot_litex |\ \ \ | * | | 2457859b - update BlackParrot transducer | * | | d2dabcef - Blackparrot human name update | |/ / * / / 188e6f57 - integration/soc/add_etherbone: pass phy to ethcore not self.ethphy. |/ / * | d5062d1f - Merge pull request #623 from Dolu1990/vexriscv_smp |\ \ | * | 07a8e696 - cpu/vexriscv_smp Add --with-coherent-dma |/ / * | 9a4c5aa1 - integration/soc/add_sdram: update rules to connect main bus to dram. * | a1644510 - cpu/vexriscv_smp: fix args_read. * | 896b68cd - cpu/vexriscv_smp: cleanup, fix coherent_dma connection. * | 342f359e - Merge pull request #622 from antmicro/fix_connectors |\ \ | * | de9ea19c - arty: Change USB-uart and I2S Pmod configuration * | | 3b293612 - soc/interconnect/axi: minor cleanups. * | | 303d6cca - interconnect/stream: set default AsyncFIFO depth to None and add depth parameter to ClockDomainCrossing. * | | 00629c45 - interconnect/csr: add CSR registers ordering support. * | | ee7a7f46 - soc/interconnect/csr: improve ident. * | | b1008b01 - integration/soc: add expection on decoder when full address space is mapped. * | | b831dc8c - wishbone: revert default adr_width to 30. | |/ |/| * | abc49964 - tools/litex_json2dts: add missing copyrights. * | aed0dcee - setup: add litex_json2dts to console_scripts. * | b64209b3 - Merge pull request #620 from antmicro/add_litex_json2dts |\ \ | * | fafa844a - json2dts: Add Linux DT generation script * | | 0ca99b79 - build/sim/config: add default_clk/default_clk_freq parameters for retro-compatibility with previous API. * | | 696ea468 - build/sim: use json_object_get_int64 instead of json_object_get_uint64. * | | 382c1a3a - Merge pull request #619 from antmicro/jboc/sim-clocker |\ \ \ | |/ / |/| | | * | f778ff09 - build/sim: improve timebase calculation (strict checks) and update modules | * | c1ae7e59 - build/sim: allow for arbitrary clocks generation using clockers | * | 38054874 - build/sim: use a real timebase in the simulation * | | e0f131a3 - cores/uart: add txempty/rxfull CSRs. * | | 2a3e39b1 - tools/litex_server: enable read_merger with CommUDP. * | | a5d0a340 - test: specify wishbone adr_width on AXI(Lite)<-->Wishbone tests and remove debug traces. * | | eb3374d0 - Merge pull request #617 from gsomlo/gls_rocket_dma |\ \ \ | * | | 561331ed - debug: make CI print offending values | * | | df3428be - liblitesdcard/sdcard: (temporarily) slow down SDCARD_CLK_FREQ to 25MHz | * | | 2d9dc8f9 - cores/cpu/rocket: expose slave port for DMA | * | | d8161e5a - integration/soc: make DMA slave region cover (at least) the lower 4GB | * | | 70eae5cb - interconnect/wishbone: increase WB address width to 31 | * | | b8c9da81 - soc/interconnect/axi: add Wishbone2AXI converter |/ / / * | | 2ec4604c - cores/gpio: add support for Record on GPIOOut, GPIOIn and GPIOInOut. * | | 5e53e5d7 - Merge pull request #615 from pepijndevos/openfpgaloader |\ \ \ | * | | 79ca4d96 - remove debugging | * | | f6e20700 - add openFPGAloader programmer * | | | eab0726c - cpu/vexriscv/core: use variant name as human_name. * | | | e0a763e5 - cpu/vexriscv/system.h: provide empty flush_cpu_i/dcache functions for variants with no i/d cache. * | | | 3ff1bcaf - cpu/zynq7000: set csr map to 0x00000000. * | | | c0253e3f - Merge pull request #611 from antmicro/jboc/axi-lite |\ \ \ \ | | |/ / | |/| | | * | | e78d950a - soc/interconnect/axi: add AXILite -> AXI converter * | | | cc844054 - tools/litex_server/read_merger: review/simplify a bit. * | | | 4f382ccf - Merge pull request #605 from cklarhorst/feature-uart-read-merger |\ \ \ \ | * | | | 2034c563 - Merge sequential reads for the UART litex_server backend * | | | | a942e358 - cpu/blackparrot: minor cleanups, add sim variant (since use different flist). | |_|_|/ |/| | | * | | | 86e910df - Merge pull request #610 from Dolu1990/vexriscv_smp |\ \ \ \ | * | | | 023ab15e - soc/cores/cpu/vexriscv_smp enable dynamic litedram datawidth | * | | | e5cd5d54 - Merge branch 'master' into vexriscv_smp | |\ \ \ \ | |/ / / / |/| | | | * | | | | 1938ce36 - integration/soc/add_sdram: allow the CPU to add the direct memory buses when adding the sdram. * | | | | 6576416b - cores/cpu/rocket: add use_memory_bus parameter to easily disable direct memory bus for testing. | * | | | 789a70e7 - Merge branch 'master' into vexriscv_smp | |\ \ \ \ | |/ / / / |/| | | | * | | | | 0696b409 - CHANGES: update. * | | | | fe38e12b - cpu/vexriscv_smp: move litedram import, remove os.path import. * | | | | 59b95fad - litex_setup: fix vexriscv-smp repository. * | | | | 9d052f38 - Merge pull request #607 from Dolu1990/vexriscv_smp |\ \ \ \ \ | | * | | | d284dfbe - soc/cores/cpu/vexriscv_smp config update | |/ / / / | * / / / aa57c7a2 - soc/cores/cpu/vexriscv_smp integration |/ / / / * | | | f87513ab - liblitesdcard/sdcard: increase SDCARD_CLK_FREQ to 50MHz. * | | | 9518ccf4 - integration/soc/etherbone: expose ethcore (useful to combine udp/etherbone). | |_|/ |/| | * | | 9e07623b - integration/soc: fix dma_bus typo. |/ / * / 1fdffdfd - targets: keep in sync with litex-boards. |/ * 8a0684b1 - Merge pull request #604 from antmicro/jboc/axi-lite |\ | * 879e6ffe - soc/interconnect/axi: add basic AXI Lite up-converter | * 32160e61 - soc/interconnect/axi: separate AXI Lite converter channels * | ed721198 - Merge pull request #603 from enjoy-digital/socdoc-extensions |\ \ | * | 29b2baf9 - doc: socdoc: document new `sphinx_extra_config` parameter | * | dd366467 - litex: add `sphinx_extra_config` to `generate_docs()` * | | 3d16838d - Merge pull request #602 from enjoy-digital/socdoc-extensions |\| | | * | 7fecfbf8 - doc: socdoc: document `sphinx_extensions` parameter |/ / * | 83370399 - CHANGES: update. * | 041c7527 - core/cpu: integrate Zynq as a classical CPU (Zynq7000), deprecate SoCZynq. |/ * 8bdf6941 - liblitesdcard/sdcard: use max divider of 256 (128 was not enough for the initial 400Khz clock frequency). * 8f92034d - CHANGES: update. * 99e88dfc - Merge pull request #600 from antmicro/jboc/axi-lite |\ | * a9d8b813 - test/axi: move all AXI Lite tests to separate file | * 367eb122 - soc/integration: use AXILiteSRAM when using bus_standard="axi-lite" | * 8ae501c3 - test/axi: add crossbar stress tests | * 706bc25d - soc/integration: add bus standard parser arguments | * 32d9e212 - soc/interconnect/axi: improve Timeout module and test it with shared interconnect | * 2cab7fbf - test/axi: add shared AXI Lite interconnect tests | * 3a08b21d - soc/interconnect/axi: implement AXI Lite decoder | * 214cfdca - soc/interconnect/axi: lock AXILiteArbiter until all requests have been responded to | * baf23c9c - test/test_axi: add AXI Lite interconnect arbiter tests | * a8a583d6 - socinterconnect/axi: interconnect shared sketch | * f47ccdae - soc/interconnect/axi: point-to-point interconnect and timeout module with tests | * b4c1120e - soc/integration: choose interconnect based on bus standard | * 69d8dd78 - soc/integration: add axi-lite standard to SoCBusHandler * | d38048ba - soc: add initial DMA bus support (optionally provided by CPU(s) for cache coherency). |/ * 2361abb1 - Merge pull request #599 from antmicro/gen-mmcm-pr |\ | * 66c5f371 - litex-gen: add mmcm core * 6b72f52c - boards: keep in sync with litex-boards. * 1f27b740 - soc/integration/add_sdcard: add direct connection to VexRiscv's dmabus for testing. * 408d1a9f - cpu/vexriscv/system.h: update flush_cpu_dcache. * 47ce15b4 - interconnect/wishbone: add minimal UpConverter. * litex-boards changed from 2ce24df to 2020.08-9-g63b65e2 * 63b65e2 - crosslink_nx_evn: update copyrights. * 153326f - targets/icebreaker: update flash. * 795e34a - add initial Crosslink-NX support. * 84c19a6 - targets/de0nano: set sys2x_ps phase to 180° for sdram_rate=1:2. * 70594a5 - ulx3s: simplify sdram constraints and increase phase to 180 for sdram_rate=1:2. * 1781be1 - general: add SPDX License identifier to header and specify files are part of LiteX-Boards. * 83d8b8d - platforms/acorn_cle_215: integrated sdcard ios as extension. * d365836 - Merge pull request #100 from connorwk/master |\ | * f328909 - Moved platform call inside of BaseSoC init for compatibility with linux-on-litex-vexriscv support. Added optional spi-sdcard support over P2 header. |/ * 45bb329 - targets/colorlight_5a_75x: enable HalfRate SDRAM PHY. * b6a1ad5 - targets/orangecrab: add simple CRG when built without DDR3. * 869cead - targets: use platform.request_all on LedChaser. * 8583c44 - Merge pull request #98 from antmicro/arty_pmod_configuration |\ | * d2cd6d4 - arty: Change USB-uart and I2S Pmod configuration |/ * ee28d7b - targets/ulx3s/add_oled: simplify. * 623faa9 - Merge pull request #96 from pepijndevos/oled |\ | * eba7037 - add optional OLED peripheral to ULX3S target |/ * 929e55d - platforms/trellisboard: add SDCard PMOD pins. * 5fd3e8d - ecpix5: add SDCard. * f058181 - README: fix typo. * 94ccf1d - targets/trellisboard: simplify clocking when no DDR3, remove firmware_ram (was here for debug). * ecdc1ef - README: add missings . * 361afa7 - README: add links to LiteX's wiki. * 02c0c0a - README: add board picture and fix a few typos. * eb8a484 - targets/de10nano: fix typo. * 2cef54a - targets/colorlight_5a_75x: avoid sys_clk_freq of 125MHz with etherbone (no longer required). * bfbee48 - Readme/boards: fill most of the missing infos. * bb65692 - add LICENSE. * e9706d4 - README: add initial contents and list of supported boards. * 760b8ff - arty: improve xy_pmod_io genericity (allow selecting the PMOD) and enable SDCard. * 04fc98f - de0nano/ulx3s: add sdram HalfRate support (untested). * d0ca1be - targets/de10nano/minispartan6: simplify HalfRate support, rename argument to sdram_rate. * 9730c6f - platforms/de10nano: use additional sdram constraints required for HalfRate. * 7399d13 - paltforms/de10nano/sdram: enable fast input/output on dq. * b4b1ab8 - paltforms/de10nano: simplify IO constraints (for consistency with others platforms). * 89c5bf4 - Merge pull request #92 from rob-ng15/master |\ | * 7cda143 - Allow use of HalfRateGENSDRPHY | * cf98393 - Add Misc * | 1e1589a - zybo_z7: demonstrate use of PS7 (with --cpu-type=zynq7000). * | 8a3b453 - add Zybo Z7 minimal platform/targets: no PS7 support and USB-UART PMOD on JB. |/ * e723bef - platforms/arty: add usb_uart_pmod_io (USB-UART PMOD on JA) to ease debug with a second UART (for UARTbone/LiteScope). * 19d0b95 - platforms/targets: keep in sync with litex. * 0ee4b21 - trellisboard/ulx3s: fix sdcard slewrate. * 7efa1c3 - platforms/arty: add missing pullups on sdcard. * litex-renode changed from f179258 to 3d01f40 * 3d01f40 - Merge pull request #29 from antmicro/i2c_generation * ed34c42 - generate-renode-scripts: Add I2C support * a431211 - generate-zephyr-dts: Add I2C support * 9f4f0fb - [FIX] Fix config generation * nmigen changed from 8f5a253 to 1ad6e32 * 1ad6e32 - Clifford -> Claire * 40f7f12 - Add option to specify solver in nmigen.test.utils Full submodule status -- 2942d0652a89646c5225bee15dd55cc3b0871766 VexRiscv (1.0.1-417-g2942d06) 3a6108a75be356a3dc53760d22782f1323248b6b edid-decode (heads/master) 3a06aa84b62ad24467fb0d2c6ceddf565e9ea447 flash_proxies (heads/master) 5c69da5d6db245dedab479509c0eaa8c1c80027c litedram (2020.08-3-g5c69da5) 54acf9fd76c226d7760294ffde86418e52e0951b liteeth (2020.04-26-g54acf9f) efd200fa9e625144131a310fc09fd1fecf1682e6 liteiclink (2020.08-1-gefd200f) 0718fd135fc30e0a3598eaf66ce2fcb54b62193c litepcie (2020.08-1-g0718fd1) ba006a78c12e25354dafb021510c043dbe070614 litesata (2020.08-1-gba006a7) 02b543e5ba24c025212515f6e32f542629d823e8 litescope (2020.08-2-g02b543e) 7457a29b1a47fe15e81fa37f3bbdd510788f1d53 liteusb (heads/master) 41f30143075ece3fff5c33a332ed067d1837cbb3 litevideo (2020.04) 3897acb9e4b91ad58abbcea8e3cff6e44223bd02 litex (2020.04-639-g3897acb9) 63b65e278c279a9cf8c4da31db8f7e845edba394 litex-boards (2020.08-9-g63b65e2) 3d01f408539b4641f9d2b42ebd8237436e49d16b litex-renode (remotes/origin/HEAD) 7bc4eb1387b39159a74c1dbd1b820728e0bfbbaa migen (0.6.dev-354-g7bc4eb1) 1ad6e3207f02e913407867dddddb8f50fad0ced4 nmigen (v0.1-71-g1ad6e32) 48333804e40c7c9c1c8d5b2e70ba75f4b646d8f0 pythondata-cpu-lm32 (2020.08) 4731142284cf87e89b21fb35ceff1139f2f89227 pythondata-cpu-minerva (2020.08) af561171f5fc8c684537897f12ef0f429e38624b pythondata-cpu-mor1kx (2020.08) 88974894c800ee2e827db47865e0611a07ff40d7 pythondata-cpu-picorv32 (2020.08) 654057b2f5cec0f9fc99487dff67861f76fcbe7e pythondata-cpu-vexriscv (2020.08) 7cfcaed2e726027fd622650b58dd77e47c495ee0 pythondata-software-compiler_rt (2020.08) da4c8c72eeb22894369b3936abb73f828f222b8e valentyusb (v0.3.3-195-gda4c8c7) --- third_party/litedram | 2 +- third_party/liteeth | 2 +- third_party/liteiclink | 2 +- third_party/litepcie | 2 +- third_party/litesata | 2 +- third_party/litescope | 2 +- third_party/litex | 2 +- third_party/litex-boards | 2 +- third_party/litex-renode | 2 +- third_party/nmigen | 2 +- 10 files changed, 10 insertions(+), 10 deletions(-) diff --git a/third_party/litedram b/third_party/litedram index f51052f8b..5c69da5d6 160000 --- a/third_party/litedram +++ b/third_party/litedram @@ -1 +1 @@ -Subproject commit f51052f8b737156d1e257eff7cd3259cb56d0d1b +Subproject commit 5c69da5d6db245dedab479509c0eaa8c1c80027c diff --git a/third_party/liteeth b/third_party/liteeth index 792013a17..54acf9fd7 160000 --- a/third_party/liteeth +++ b/third_party/liteeth @@ -1 +1 @@ -Subproject commit 792013a1756ea50608726ee86989ec38cfc35a8b +Subproject commit 54acf9fd76c226d7760294ffde86418e52e0951b diff --git a/third_party/liteiclink b/third_party/liteiclink index 6fdd02058..efd200fa9 160000 --- a/third_party/liteiclink +++ b/third_party/liteiclink @@ -1 +1 @@ -Subproject commit 6fdd02058fba29008c90b162e0ef707dce15ebeb +Subproject commit efd200fa9e625144131a310fc09fd1fecf1682e6 diff --git a/third_party/litepcie b/third_party/litepcie index 0b6a4bb6e..0718fd135 160000 --- a/third_party/litepcie +++ b/third_party/litepcie @@ -1 +1 @@ -Subproject commit 0b6a4bb6e742fd4de38d7ca3674f91acc5985b35 +Subproject commit 0718fd135fc30e0a3598eaf66ce2fcb54b62193c diff --git a/third_party/litesata b/third_party/litesata index b36d3a33f..ba006a78c 160000 --- a/third_party/litesata +++ b/third_party/litesata @@ -1 +1 @@ -Subproject commit b36d3a33fbbfcffdb77a7a9e05bc8121387858d3 +Subproject commit ba006a78c12e25354dafb021510c043dbe070614 diff --git a/third_party/litescope b/third_party/litescope index 15179cb46..02b543e5b 160000 --- a/third_party/litescope +++ b/third_party/litescope @@ -1 +1 @@ -Subproject commit 15179cb46f68bff1679631a8bade6f7e1607a40a +Subproject commit 02b543e5ba24c025212515f6e32f542629d823e8 diff --git a/third_party/litex b/third_party/litex index 9fc488bdf..3897acb9e 160000 --- a/third_party/litex +++ b/third_party/litex @@ -1 +1 @@ -Subproject commit 9fc488bdf670c69193a6fa14e5f0c218db8b0ffe +Subproject commit 3897acb9e4b91ad58abbcea8e3cff6e44223bd02 diff --git a/third_party/litex-boards b/third_party/litex-boards index 2ce24df76..63b65e278 160000 --- a/third_party/litex-boards +++ b/third_party/litex-boards @@ -1 +1 @@ -Subproject commit 2ce24df76dda20cff9ac40c334300d5dc1311d60 +Subproject commit 63b65e278c279a9cf8c4da31db8f7e845edba394 diff --git a/third_party/litex-renode b/third_party/litex-renode index f1792587a..3d01f4085 160000 --- a/third_party/litex-renode +++ b/third_party/litex-renode @@ -1 +1 @@ -Subproject commit f1792587a9b50732578e0166cb5d1d83b126cfa6 +Subproject commit 3d01f408539b4641f9d2b42ebd8237436e49d16b diff --git a/third_party/nmigen b/third_party/nmigen index 8f5a253b2..1ad6e3207 160000 --- a/third_party/nmigen +++ b/third_party/nmigen @@ -1 +1 @@ -Subproject commit 8f5a253b22cd4ebcd56304a3662f4c70e3b34ed5 +Subproject commit 1ad6e3207f02e913407867dddddb8f50fad0ced4