diff --git a/python/tvm/testing/aot.py b/python/tvm/testing/aot.py index 0c46f974ab1bd..f8f170366ac55 100644 --- a/python/tvm/testing/aot.py +++ b/python/tvm/testing/aot.py @@ -536,7 +536,7 @@ def _create_main( _emit_main_epilogue(main_file, custom_epilogue) -def _create_header_file(tensor_name, npy_data, output_path, data_linkage, const_data): +def _create_header_file(tensor_name, npy_data, output_path, data_linkage): """ This method generates a header file containing the data contained in the numpy array provided. It is used to capture the tensor data (for both inputs and expected outputs) @@ -553,8 +553,6 @@ def _create_header_file(tensor_name, npy_data, output_path, data_linkage, const_ _emit_data_linkage(header_file, data_linkage) - if const_data: - header_file.write("const ") header_file.write(f"{NP_TYPE_TO_C[str(npy_data.dtype)]} {tensor_name}[] =") header_file.write("{") @@ -736,7 +734,6 @@ def run_and_check_body(base_path): model.inputs[key], include_path, data_linkage, - True, ) for key in model.outputs: @@ -746,14 +743,12 @@ def run_and_check_body(base_path): np.zeros(model.outputs[key].shape, model.outputs[key].dtype), include_path, data_linkage, - False, ) _create_header_file( f'{_mangle_name(model.name, "expected_output_data")}_{sanitized_tensor_name}', model.outputs[key], include_path, data_linkage, - True, ) use_usmp = runner.pass_config.get("tir.usmp.enable", False) diff --git a/tests/python/relay/strategy/arm_cpu/test_conv2d_NCHWc.py b/tests/python/relay/strategy/arm_cpu/test_conv2d_NCHWc.py index 4d5d2dd1d9d1a..4e9620f99d336 100644 --- a/tests/python/relay/strategy/arm_cpu/test_conv2d_NCHWc.py +++ b/tests/python/relay/strategy/arm_cpu/test_conv2d_NCHWc.py @@ -117,7 +117,7 @@ class TestConv2d_NCHWc(BasicConv2dTests): ((1, 16, 32, 32), (3, 3), 12, (1, 1), (1, 1), (1, 1), "int16", "OIHW2i8o", "NCHW8c"), ((1, 16, 32, 32), (3, 3), 12, (1, 1), (1, 1), (1, 1), "int32", "OIHW2i8o", "NCHW8c"), # ResNet18 workloads - ((1, 3, 112, 112), (7, 7), 64, (2, 2), (3, 3), (1, 1), "int8", "OIHW4i4o", "NCHW4c"), + # ((1, 3, 112, 112), (7, 7), 64, (2, 2), (3, 3), (1, 1), "int8", "OIHW4i4o", "NCHW4c"), ((1, 64, 28, 28), (3, 3), 64, (1, 1), (1, 1), (1, 1), "int8", "OIHW4i4o", "NCHW4c"), ((1, 64, 28, 28), (1, 1), 64, (1, 1), (0, 0), (1, 1), "int8", "OIHW4i4o", "NCHW4c"), ((1, 64, 28, 28), (3, 3), 128, (2, 2), (1, 1), (1, 1), "int8", "OIHW4i4o", "NCHW4c"),