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NOR gate mapping #277

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Maya7991 opened this issue Feb 4, 2024 · 1 comment
Open

NOR gate mapping #277

Maya7991 opened this issue Feb 4, 2024 · 1 comment

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@Maya7991
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Maya7991 commented Feb 4, 2024

From an input BLIF file, I want to generate a gate level Verilog file that has only NOR gates . Can someone help me with the commands to be followed for this in ABC
@JiaxiangPan
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I think this repository might be able to help you: https://github.com/debjyoti0891/MAGICNetlistGen

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@JiaxiangPan @Maya7991