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Symbiflow-classroom: Surelog/UHDM and multi-bit input signals #269
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It does indeed seem to be a bug in Surelog. Filed an issue: chipsalliance/Surelog#2733 |
The Surelog issue was resolved, but we need to update the plugin to use the newest version. We'll let you know when it's done. |
Surelog was updated, this should work now (the AST from plugin looks correct). |
@rkapuscik Thanks - I will test it as soon as I can verify it is available. When you say Surelog is updated, what do you mean? Will we get it if we simply re-install f4pga-examples. Or, is there additional work needed to pull it over into f4pga-examples so my student can use it to test with? |
Sorry that I wasn't clear enough. By updating Surelog, I mean that
Reinstalling f4pga-examples will give you the updated version, but you can also update just the conda environment:
If anything goes wrong, you can also remove and recreate it by
This should give you the updated tools. You can verify which version you have installed by
|
@rkapuscik Thanks! Have verified it works, closing issue. |
SYMBIFLOW-CLASSROOM-PROJECT
Using Surelog/UHDM front end. Obtained from cloning f4pga-examples and then doing:
Attached is a simple design that compiles successfully using
yosys standard frontend. All it does is turn on LEDs when switches are flipped.
This design compiles successfully using SURELOG/UHDM if, instead of naming the
input logic ports iteritavely (sw[0],sw[1],sw[2]),
they are named uniquely (A,B,C).
The issue is shown in compile.log that by the time that the design reaches
Yosys AST, the switch ports have already been flattened which suggests that the
issue resides in Surelog or UHDM.
SwitchBug.zip
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