counter_test Demo for zybo build failed for the directory path mistakes

[tonyho]

I following the user guide to build the counter_test demo for zybo, which would give errors:

3. Executing Verilog-2005 frontend: /home/hexiongjun/opt/f4pga/xc7/conda/envs/xc7/bin/../share/yosys/xilinx/cells_xtra.v
Parsing Verilog input from `/home/hexiongjun/opt/f4pga/xc7/conda/envs/xc7/bin/../share/yosys/xilinx/cells_xtra.v' to AST representation.
Generating RTLIL representation for module `\RAMB4_S1'.
Generating RTLIL representation for module `\RAMB4_S2'.
Generating RTLIL representation for module `\RAMB4_S4'.
Generating RTLIL representation for module `\RAMB4_S8'.
Generating RTLIL representation for module `\RAMB4_S16'.
Generating RTLIL representation for module `\RAMB4_S1_S1'.
Generating RTLIL representation for module `\RAMB4_S1_S2'.
Generating RTLIL representation for module `\RAMB4_S1_S4'.
Generating RTLIL representation for module `\RAMB4_S1_S8'.
Generating RTLIL representation for module `\RAMB4_S1_S16'.
...
...
Generating RTLIL representation for module `\ILKN'.
Generating RTLIL representation for module `\ILKNE4'.
Generating RTLIL representation for module `\VCU'.
Generating RTLIL representation for module `\FE'.
Successfully finished Verilog frontend.
ERROR: Can't open input file `/home/hexiongjun/opt/f4pga/xc7/share/f4pga/techmaps/xc7_vpr/techmap/iobs.v' for reading: No such file or directory
ERROR: TCL interpreter returned an error: Yosys command produced an error
Traceback (most recent call last):
  File "/home/hexiongjun/opt/f4pga/xc7/conda/envs/xc7/bin/symbiflow_synth", line 8, in <module>
    sys.exit(synth())
  File "/home/hexiongjun/opt/f4pga/xc7/conda/envs/xc7/lib/python3.7/site-packages/f4pga/wrappers/sh/__init__.py", line 571, in synth
    p_run_sh_script(ROOT / SH_SUBDIR / "synth.f4pga.sh", env=env)
  File "/home/hexiongjun/opt/f4pga/xc7/conda/envs/xc7/lib/python3.7/site-packages/f4pga/wrappers/sh/__init__.py", line 51, in p_run_sh_script
    check_call([str(script)] + sys_argv[1:], env=env)
  File "/home/hexiongjun/opt/f4pga/xc7/conda/envs/xc7/lib/python3.7/subprocess.py", line 363, in check_call
    raise CalledProcessError(retcode, cmd)
subprocess.CalledProcessError: Command '['/home/hexiongjun/opt/f4pga/xc7/conda/envs/xc7/lib/python3.7/site-packages/f4pga/wrappers/sh/xc7/synth.f4pga.sh', '-t', 'top', '-v', '/home/hexiongjun/github/f4pga-examples/xc7/counter_test/counter_zynq.v', '-d', 'zynq7', '-p', 'xc7z010clg400-1', '-x', '/home/hexiongjun/github/f4pga-examples/xc7/counter_test/zybo.xdc']' returned non-zero exit status 1.
make: *** [/home/hexiongjun/github/f4pga-examples/xc7/counter_test/../../common/common.mk:67: /home/hexiongjun/github/f4pga-examples/xc7/counter_test/build/zybo/top.eblif] Error 1
make: Leaving directory '/home/hexiongjun/github/f4pga-examples/xc7/counter_test'

and the other error log:

54. Executing BLIF backend.

Warnings: 67 unique messages, 68 total
End of script. Logfile hash: 58d5cd1695, CPU: user 10.20s system 0.16s, MEM: 342.66 MB peak
Yosys 0.27+22 (git sha1 0f5e7c244, x86_64-conda-linux-gnu-cc 11.2.0 -fvisibility-inlines-hidden -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fst
ack-protector-strong -fno-plt -O2 -ffunction-sections -fdebug-prefix-map=/root/conda-eda/conda-eda/workdir/conda-env/conda-bld/yosys_1680770278298/work=/usr/local/src/cond
a/yosys-0.27_29_g0f5e7c244 -fdebug-prefix-map=/home/hexiongjun/opt/f4pga/xc7/conda/envs/xc7=/usr/local/src/conda-prefix -fPIC -Os -fno-merge-constants)
Time spent: 45% 45x read_verilog (5 sec), 20% 1x tcl (2 sec), ...
cd /home/hexiongjun/github/f4pga-examples/xc7/counter_test/build/zybo && symbiflow_pack -e top.eblif -d xc7z010_test  2>&1 > /dev/null
Error 1: /home/hexiongjun/opt/f4pga/xc7/share/f4pga/arch/xc7z010_test/arch.timing.xml:-1 Failed to open file
Traceback (most recent call last):
  File "/home/hexiongjun/opt/f4pga/xc7/conda/envs/xc7/bin/symbiflow_pack", line 8, in <module>
    sys.exit(pack())
  File "/home/hexiongjun/opt/f4pga/xc7/conda/envs/xc7/lib/python3.7/site-packages/f4pga/wrappers/sh/__init__.py", line 502, in pack
    p_vpr_run(["--pack"] + extra_args, env=p_vpr_env_from_args("pack"))
  File "/home/hexiongjun/opt/f4pga/xc7/conda/envs/xc7/lib/python3.7/site-packages/f4pga/wrappers/sh/__init__.py", line 135, in p_vpr_run
    + args,
  File "/home/hexiongjun/opt/f4pga/xc7/conda/envs/xc7/lib/python3.7/subprocess.py", line 363, in check_call
    raise CalledProcessError(retcode, cmd)
subprocess.CalledProcessError: Command '['/home/hexiongjun/opt/f4pga/xc7/conda/envs/xc7/bin/vpr', '/home/hexiongjun/opt/f4pga/xc7/share/f4pga/arch/xc7z010_test/arch.timing.xml', 'top.eblif', '--max_router_iterations', '500', '--routing_failure_predictor', 'off', '--router_high_fanout_threshold', '-1', '--constant_net_method', 'route', '--route_chan_width', '500', '--router_heap', 'bucket', '--clock_modeling', 'route', '--place_delta_delay_matrix_calculation_method', 'dijkstra', '--place_delay_model', 'delta', '--router_lookahead', 'extended_map', '--check_route', 'quick', '--strict_checks', 'off', '--allow_dangling_combinational_nodes', 'on', '--disable_errors', 'check_unbuffered_edges:check_route', '--congested_routing_iteration_threshold', '0.8', '--incremental_reroute_delay_ripup', 'off', '--base_cost_type', 'delay_normalized_length_bounded', '--bb_factor', '10', '--acc_fac', '0.7', '--astar_fac', '1.8', '--initial_pres_fac', '2.828', '--pres_fac_mult', '1.2', '--check_rr_graph', 'off', '--suppress_warnings', 'noisy_warnings-xc7z010_test_pack.log,sum_pin_class:check_unbuffered_edges:load_rr_indexed_data_T_values:check_rr_node:trans_per_R:check_route:set_rr_graph_tool_comment:calculate_average_switch', '--device', 'xc7z010-test', '--read_rr_graph', '/home/hexiongjun/opt/f4pga/xc7/share/f4pga/arch/xc7z010_test/rr_graph_xc7z010_test.rr_graph.real.bin', '--read_router_lookahead', '/home/hexiongjun/opt/f4pga/xc7/share/f4pga/arch/xc7z010_test/rr_graph_xc7z010_test.lookahead.bin', '--read_placement_delay_lookup', '/home/hexiongjun/opt/f4pga/xc7/share/f4pga/arch/xc7z010_test/rr_graph_xc7z010_test.place_delay.bin', '--pack']' returned non-zero exit status 1.
make: *** [/home/hexiongjun/github/f4pga-examples/xc7/counter_test/../../common/common.mk:71: /home/hexiongjun/github/f4pga-examples/xc7/counter_test/build/zybo/top.net] Error 1
make: Leaving directory '/home/hexiongjun/github/f4pga-examples/xc7/counter_test'

I resolve this by creating several symbol links for directories:

mkdir ~/opt/f4pga/xc7/share
mkdir ~/opt/f4pga/xc7/share/f4pga
ln -s ~/opt/f4pga/xc7/install/share/symbiflow/techmaps ~/opt/f4pga/xc7/share/f4pga/techmaps

cd ~/opt/f4pga/xc7/share/f4pga
ln -s ~/opt/f4pga/xc7/install/share/symbiflow/arch arch
ln -s ~/opt/f4pga/xc7/install/share/symbiflow/scripts scripts
ln -s ~/opt/f4pga/xc7/install/share/symbiflow/techmaps techmaps

After adding such symbol links, the build passed with building bit file.