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amd_reg.h
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amd_reg.h
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/*
* CoreFreq
* Copyright (C) 2015-2024 CYRIL COURTIAT
* Licenses: GPL2
*/
#ifndef PCI_VENDOR_ID_HYGON
#define PCI_VENDOR_ID_HYGON 0x1d94
#endif
#ifndef MSR_AMD_SPEC_CTRL
#define MSR_AMD_SPEC_CTRL 0x00000048
#endif
#ifndef MSR_AMD_PRED_CMD
#define MSR_AMD_PRED_CMD 0x00000049
#endif
#ifndef MSR_AMD_F17H_MPERF
#define MSR_AMD_F17H_MPERF 0xc00000e7
#endif
#ifndef MSR_AMD_F17H_APERF
#define MSR_AMD_F17H_APERF 0xc00000e8
#endif
#ifndef MSR_F17H_IRPERF
#define MSR_AMD_F17H_IRPERF 0xc00000e9
#else
#define MSR_AMD_F17H_IRPERF MSR_F17H_IRPERF
#endif
#define MSR_AMD_PREFETCH_CTRL 0xc0000108
#ifndef MSR_AMD64_SYSCFG
#define MSR_AMD64_SYSCFG 0xc0010010
#endif
#ifndef MSR_AMD_PSTATE_CURRENT_LIMIT
#define MSR_AMD_PSTATE_CURRENT_LIMIT 0xc0010061
#endif
#ifndef MSR_AMD_PERF_CTL
#define MSR_AMD_PERF_CTL 0xc0010062
#endif
#ifndef MSR_AMD_PERF_STATUS
#define MSR_AMD_PERF_STATUS 0xc0010063
#endif
#ifndef MSR_AMD_PSTATE_DEF_BASE
#define MSR_AMD_PSTATE_DEF_BASE 0xc0010064
#endif
#ifndef MSR_AMD_COFVID_STATUS
#define MSR_AMD_COFVID_STATUS 0xc0010071
#endif
#ifndef MSR_AMD_CSTATE_BAR
#define MSR_AMD_CSTATE_BAR 0xc0010073
#endif
#define MSR_AMD_CPU_WDT_CFG 0xc0010074
#ifndef MSR_VM_CR
#define MSR_VM_CR 0xc0010114
#endif
#ifndef MSR_SVM_LOCK_KEY
#define MSR_SVM_LOCK_KEY 0xc0010118
#endif
#define MSR_AMD_F17H_PERF_CTL 0xc0010200
#define MSR_AMD_F17H_PERF_CTR 0xc0010201
#define MSR_AMD_F17H_L3_PERF_CTL 0xc0010230
#define MSR_AMD_F17H_L3_PERF_CTR 0xc0010231
#define MSR_AMD_F17H_DF_PERF_CTL 0xc0010240
#define MSR_AMD_F17H_DF_PERF_CTR 0xc0010241
#define MSR_AMD_F17H_PMGT_MISC 0xc0010292
#define MSR_AMD_F17H_HW_PSTATE_STATUS 0xc0010293
#define MSR_AMD_F17H_CSTATE_POLICY 0xc0010294
#define MSR_AMD_F17H_CSTATE_CONFIG 0xc0010296
#define MSR_AMD_F17H_PMGT_DEFAULT 0xc0010297
#ifndef MSR_AMD_RAPL_POWER_UNIT
#define MSR_AMD_RAPL_POWER_UNIT 0xc0010299
#endif
#ifndef MSR_AMD_PKG_ENERGY_STATUS
#define MSR_AMD_PKG_ENERGY_STATUS 0xc001029b
#endif
#ifndef MSR_AMD_PP0_ENERGY_STATUS
#define MSR_AMD_PP0_ENERGY_STATUS 0xc001029a
#endif
#ifndef MSR_AMD_PPIN_CTL
#define MSR_AMD_PPIN_CTL 0xc00102f0
#endif
#ifndef MSR_AMD_PPIN
#define MSR_AMD_PPIN 0xc00102f1
#endif
#ifndef MSR_AMD64_LS_CFG
#define MSR_AMD64_LS_CFG 0xc0011020
#endif
#ifndef MSR_AMD_IC_CFG
#define MSR_AMD_IC_CFG 0xc0011021
#endif
#ifndef MSR_AMD_DC_CFG
#define MSR_AMD_DC_CFG 0xc0011022
#endif
#define MSR_AMD_TW_CFG 0xc0011023
#ifndef MSR_AMD64_DE_CFG
#define MSR_AMD64_DE_CFG 0xc0011029
#endif
#ifndef MSR_AMD64_BU_CFG2
#define MSR_AMD64_BU_CFG2 0xc001102a
#endif
#ifndef MSR_AMD_CU_CFG3
#define MSR_AMD_CU_CFG3 0xc001102b
#endif
/* Sources: TECHNICAL GUIDANCE FOR MITIGATING BRANCH TYPE CONFUSION */
#ifndef MSR_AMD_DE_CFG2
#define MSR_AMD_DE_CFG2 0xc00110e3
#endif
/* Sources: 56569-A1 Rev 3.03 - PPR for AMD Family 19h Model 51h A1 */
#ifndef MSR_AMD_CPPC_CAP1
#define MSR_AMD_CPPC_CAP1 0xc00102b0
#endif
#ifndef MSR_AMD_CPPC_ENABLE
#define MSR_AMD_CPPC_ENABLE 0xc00102b1
#endif
#ifndef MSR_AMD_CPPC_CAP2
#define MSR_AMD_CPPC_CAP2 0xc00102b2
#endif
#ifndef MSR_AMD_CPPC_REQ
#define MSR_AMD_CPPC_REQ 0xc00102b3
#endif
#ifndef MSR_AMD_CPPC_STATUS
#define MSR_AMD_CPPC_STATUS 0xc00102b4
#endif
/* Sources: BKDG for AMD Family 0Fh,15_00h-15_0Fh,15_10h-15_1Fh,15_30-15_3Fh */
#define PCI_AMD_TEMPERATURE_TCTL PCI_CONFIG_ADDRESS(0, 0x18, 0x3, 0xa4)
#define PCI_AMD_THERMTRIP_STATUS PCI_CONFIG_ADDRESS(0, 0x18, 0x3, 0xe4)
/* BKDG for AMD Family [15_00h - 15_0Fh]
D18F3x1D4 Probe Filter Control
D18F3x1C4 L3 Cache Parameter
*/
#define PCI_AMD_PROBE_FILTER_CTRL PCI_CONFIG_ADDRESS(0, 0x18, 0x3, 0x1d4)
#define PCI_AMD_L3_CACHE_PARAMETER PCI_CONFIG_ADDRESS(0, 0x18, 0x3, 0x1c4)
/* Sources:
* BKDG for AMD Family [15_60h - 15_70h]
SMU index/data pair registers, D0F0xB8 and D0F0xBC
* BKDG for AMD Family 16h
D0F0x60: miscellaneous index to access the registers at D0F0x64_x[FF:00]
*/
#define SMU_AMD_INDEX_REGISTER_F15H PCI_CONFIG_ADDRESS(0, 0, 0, 0xb8)
#define SMU_AMD_DATA_REGISTER_F15H PCI_CONFIG_ADDRESS(0, 0, 0, 0xbc)
#define SMU_AMD_INDEX_PORT_F17H 0x60
#define SMU_AMD_DATA_PORT_F17H 0x64
#define SMU_AMD_INDEX_REGISTER_F17H \
PCI_CONFIG_ADDRESS(0, 0, 0, SMU_AMD_INDEX_PORT_F17H)
#define SMU_AMD_DATA_REGISTER_F17H \
PCI_CONFIG_ADDRESS(0, 0, 0, SMU_AMD_DATA_PORT_F17H)
#define AMD_HSMP_INDEX_PORT 0xc4
#define AMD_HSMP_DATA_PORT 0xc8
#define AMD_HSMP_INDEX_REGISTER \
PCI_CONFIG_ADDRESS(0, 0, 0, AMD_HSMP_INDEX_PORT)
#define AMD_HSMP_DATA_REGISTER \
PCI_CONFIG_ADDRESS(0, 0, 0, AMD_HSMP_DATA_PORT)
/* Sources:
* BKDG for AMD Family [15_60h - 15_70h]
D0F0xBC_xD820_0CA4 Reported Temperature Control
* OSRR for AMD Family 17h processors / Memory Map - SMN
59800h: SMU::THM
*/
#define SMU_AMD_THM_TRIP_REGISTER_F15H 0xd8200ce4
#define SMU_AMD_THM_TCTL_REGISTER_F15H 0xd8200ca4
#define SMU_AMD_THM_TCTL_REGISTER_F17H 0x00059800
/* Sources: PPR for AMD Family 19h Model 51h A1 : REGx59800...x59B14 */
#define SMU_AMD_THM_TCTL_CCD_REGISTER_F17H 0x00059954
#define SMU_AMD_THM_TCTL_CCD_REGISTER_F19H_61H \
(SMU_AMD_THM_TCTL_REGISTER_F17H + 0x308)
#define SMU_AMD_F17H_ZEN2_MCM_PWR 0x0005d2b4
#define SMU_AMD_F17H_ZEN2_MCM_TDP 0x0005d2b8
#define SMU_AMD_F17H_ZEN2_MCM_EDC 0x0005d2bc
#define SMU_AMD_F17H_MATISSE_COF 0x0005d2c4
#define SMU_AMD_F17H_ZEN2_MCM_COF 0x0005d324
/* Sources: PPR Vol 2 for AMD Family 19h Model 01h B1 */
#define SMU_HSMP_CMD 0x3b10534
#define SMU_HSMP_ARG 0x3b109e0
#define SMU_HSMP_RSP 0x3b10980
enum HSMP_FUNC {
HSMP_TEST_MSG = 0x1, /* Returns [ARG0] + 1 */
HSMP_RD_SMU_VER = 0x2, /* SMU FW Version */
HSMP_RD_VERSION = 0x3, /* Interface Version */
HSMP_RD_CUR_PWR = 0x4, /* Current Socket power (mWatts) */
HSMP_WR_PKG_PL1 = 0x5, /* Input within [31:0]; Limit (mWatts) */
HSMP_RD_PKG_PL1 = 0x6, /* Returns Socket power limit (mWatts) */
HSMP_RD_MAX_PPT = 0x7, /* Max Socket power limit (mWatts) */
HSMP_WR_SMT_BOOST=0x8, /* ApicId[31:16], Max Freq. (MHz)[15:0] */
HSMP_WR_ALL_BOOST=0x9, /* Max Freq. (MHz)[15:0] for ALL */
HSMP_RD_SMT_BOOST=0xa, /* Input ApicId[15:0]; Dflt Fmax[15:0] */
HSMP_RD_PROCHOT = 0xb, /* 1 = PROCHOT is asserted */
HSMP_WR_XGMI_WTH= 0xc, /* 0 = x2, 1 = x8, 2 = x16 */
HSMP_RD_APB_PST = 0xd, /* Data Fabric P-state[7-0]={0,1,2,3} */
HSMP_ENABLE_APB = 0xe, /* Data Fabric P-State Performance Boost*/
HSMP_RD_DF_MCLK = 0xf, /* FCLK[ARG:0], MEMCLK[ARG:1] (MHz) */
HSMP_RD_CCLK = 0x10, /* CPU core clock limit (MHz) */
HSMP_RD_PC0 = 0x11, /* Socket C0 Residency (100%) */
HSMP_WR_DPM_LCLK= 0x12, /* NBIO[24:16]; Max[15:8], Min[7:0] DPM */
HSMP_RESERVED = 0x13,
HSMP_RD_DDR_BW = 0x14 /* Max[31:20];Usage{Gbps[19:8],Pct[7:0]}*/
};
enum {
HSMP_UNSPECIFIED= 0x0,
HSMP_RESULT_OK = 0x1,
HSMP_FAIL_BGN = 0x2,
HSMP_FAIL_END = 0xfd,
HSMP_INVAL_MSG = 0xfe,
HSMP_INVAL_INPUT= 0xff
};
#define IS_HSMP_OOO(_rx) (_rx == HSMP_UNSPECIFIED \
|| (_rx >= HSMP_FAIL_BGN && _rx <= HSMP_FAIL_END))
/* Sources: BKDG for AMD Families 0Fh, 10h up to 16h */
const struct {
unsigned int MCF,
PCF[5];
} VCO[0b1000] = {
/* FID */
/* 000000b */ { 8, { 0, 0, 16, 17, 18}},
/* 000001b */ { 9, {16, 17, 18, 19, 20}},
/* 000010b */ {10, {18, 19, 20, 21, 22}},
/* 000011b */ {11, {20, 21, 22, 23, 24}},
/* 000100b */ {12, {22, 23, 24, 25, 26}},
/* 000101b */ {13, {24, 25, 26, 27, 28}},
/* 000110b */ {14, {26, 27, 28, 29, 30}},
/* 000111b */ {15, {28, 29, 30, 31, 32}},
};
typedef union
{ /* Speculative Control: SMT MSR 0x00000048 */
unsigned long long value;
struct
{
unsigned long long
IBRS : 1-0, /*RW: Indirect Branch Restriction Speculation*/
STIBP : 2-1, /*RW: Single Thread Indirect Branch Predictor*/
SSBD : 3-2, /*RW: Speculative Store Bypass Disable */
Reserved1 : 7-3,
PSFD : 8-7, /* RW: Predictive Store Forwarding Disable */
Reserved2 : 64-8;
};
} AMD_SPEC_CTRL;
typedef union
{ /* Speculative Control: Per Core MSR 0x00000049 iff CPUID:IBPB */
unsigned long long value;
struct
{
unsigned long long
IBPB : 1-0, /* WO: Indirect Branch Prediction Barrier */
Reserved : 64-1;
};
} AMD_PRED_CMD;
typedef union
{ /* MSR 0xc0000108 supported iff CPUID_Fn80000021_EAX[13] */
unsigned long long value;
struct
{ /* Scope[Core] */
unsigned long long
L1Stream : 1-0,
L1Stride : 2-1,
L1Region : 3-2,
L2Stream : 4-3,
ReservedBits1 : 5-4,
UpDown : 6-5,
ReservedBits2 : 64-6;
}; /* F19_M01, F19_M61, EPYC 9004 */
} AMD_PREFETCH_CONTROL;
typedef union
{
unsigned long long value;
struct
{
unsigned long long
SmmLock : 1-0, /* SMM Configuration Lock. */
Reserved1 : 3-1,
TlbCacheDis : 4-3, /* Cacheable Memory Disable. */
INVDWBINVD : 5-4, /* INVD to WBINVD Conversion. */
Reserved2 : 7-5,
AllowFerrOnNe : 8-7, /* Allow FERR on NE.. */
IgnneEm : 9-8, /* IGNNE port emulation enable. */
MonMwaitDis : 10-9, /* 1=MONITOR & MWAIT opcodes become invalid. */
MonMwaitUserEn : 11-10, /* MONITOR/MWAIT user mode enable. 0=pl0 only*/
Reserved3 : 12-11,
HltXSpCycEn : 13-12, /* halt-exit special bus cycle enable. */
SmiSpCycDis : 14-13, /* SMI special bus cycle disable. */
RsmSpCycDis : 15-14, /* RSM special bus cycle disable. */
Reserved4 : 17-15,
Wrap32Dis : 18-17, /* 32-bit address wrap disable. */
McStatusWrEn : 19-18, /* Machine check status write enable. */
Reserved5 : 20-19,
IoCfgGpFault : 21-20, /* IO-space configuration causes a GP fault. */
Reserved6 : 23-21,
ForceRdWrSzPrb : 24-23, /* Force probes for RdSized and WrSized. */
TscFreqSel : 25-24, /* 1=The TSC increments at the P0 frequency. */
CpbDis : 26-25, /* 1=Core performance boost disable. */
EffFreqCntMwait : 27-26, /* Effective frequency counting during mwait.*/
/* Family 15h */
EffFreqROLock : 28-27, /* Read-only effective frequency counter lock*/
SmuLock : 29-28,
CSEnable : 30-29, /* Connected standby enable. */
Reserved7 : 32-30,
Reserved : 64-32;
} Family_12h;
struct
{
unsigned long long
SmmLock : 1-0, /* RWO: BIOS SMM code lock */
Reserved1 : 3-1,
TlbCacheDis : 4-3, /* RW: 1=Disable cacheable PML4,PDP,PDE,PTE */
INVDWBINVD : 5-4, /* RW: 1=Convert INVD to WBINVD */
Reserved2 : 7-5,
AllowFerrOnNe : 8-7, /* RW: 1=Legacy FERR signaling/exception */
IgnneEm : 9-8, /* RW: 1=Enable emulation of IGNNE port */
MonMwaitDis : 10-9, /* RW: 1=Disable MONITOR & MWAIT opcodes */
MonMwaitUserEn : 11-10, /* RW: 1=MONITOR/MWAIT all privilege levels */
Reserved3 : 13-11,
SmiSpCycDis : 14-13, /* 0=Generate SMI special bus cycle */
RsmSpCycDis : 15-14, /* 0=Generate RSM special bus cycle */
Reserved4 : 17-15,
Wrap32Dis : 18-17, /* RW: 1=Above 4GB Memory in 32-bits mode */
McStatusWrEn : 19-18, /* RW: 1=Machine Check status writeable */
Reserved5 : 20-19,
IoCfgGpFault : 21-20, /* RW: 1=IO-space config. causes GP fault */
LockTscToCurrP0 : 22-21, /* RW: 1=Lock TSC to current P0 frequency */
Reserved6 : 24-22,
TscFreqSel : 25-24, /* RO: 1=TSC increments at the P0 frequency */
CpbDis : 26-25, /* RW: 1=Core Performance Boost disable */
EffFreqCntMwait : 27-26, /* RW: A-M-Perf increment during MWAIT */
EffFreqROLock : 28-27, /* W1: Lock A-M-Perf & IR-Perf counters */
Reserved7 : 29-28,
CSEnable : 30-29,
IRPerfEn : 31-30, /* RW: Enable Instructions Retired counter */
SmmBaseLock : 32-31, /* MSR SMM_BASE saved/restored from save area*/
TprLoweringDis : 33-32, /* RW: FastTprLoweringDis: 1=Disabled */
SmmPgCfgLock : 34-33, /* SMM reserved and iff 8000_0021_EAX[3] */
Reserved8 : 35-34,
CpuidUserDis : 36-35, /* CPUID User Disable iff 8000_0021_EAX[17] */
Reserved9 : 64-36;
} Family_17h;
struct
{
unsigned long long
SmmLock : 1-0,
SLOWFENCE : 2-1, /* Slow SFENCE Enable. */
Reserved1 : 3-2,
TlbCacheDis : 4-3,
INVDWBINVD : 5-4, /* This bit is required to be set for CC6 */
Reserved2 : 6-5,
FFDIS : 7-6, /* TLB Flush Filter Disable. */
DISLOCK : 8-7, /* Disable x86 LOCK prefix functionality. */
IgnneEm : 9-8,
Reserved3 : 12-9,
HltXSpCycEn : 13-12,
SmiSpCycDis : 14-13,
RsmSpCycDis : 15-14,
SSEDIS : 16-15, /* SSE Instructions Disable. */
Reserved4 : 17-16,
Wrap32Dis : 18-17,
McStatusWrEn : 19-18,
Reserved5 : 24-19,
StartFID : 30-24, /* Startup FID Status. */
Reserved6 : 32-30,
Reserved : 64-32;
} Family_0Fh;
} HWCR;
typedef union
{
unsigned long long value;
struct
{
unsigned long long
NewFID : 6-0,
Reserved1 : 8-6,
NewVID : 14-8,
Reserved2 : 16-14,
InitFidVid : 17-16, /* Initiate FID/VID Change */
Reserved3 : 32-17,
StpGntTOCnt : 52-32, /* Stop Grant Time-Out Count */
Reserved4 : 64-52;
};
} FIDVID_CONTROL;
typedef union
{
unsigned long long value;
struct
{
unsigned long long
CurrFID : 6-0, /* Current FID */
Reserved1 : 8-6,
StartFID : 14-8, /* Startup FID */
Reserved2 : 16-14,
MaxFID : 22-16, /* Max FID */
Reserved3 : 24-22,
MaxRampVID : 30-24, /* Max Ramp VID */
Reserved4 : 31-30,
FidVidPending : 32-31, /* 0b when the FID/VID change has completed.*/
CurrVID : 38-32, /* Current VID */
Reserved5 : 40-38,
StartVID : 46-40, /* Startup VID */
Reserved6 : 48-46,
MaxVID : 54-48, /* Max VID */
Reserved7 : 56-54,
PstateStep : 57-56, /* voltage reduction: 0b=25mV; 1b=50mV */
AltVidOffset : 60-57, /* [NA;-50;-100;-125;-150;-175;-200;-225]mV */
Reserved8 : 61-60,
IntPstateSup : 62-61, /* 1b = Intermediate P-states is supported. */
Reserved9 : 64-62;
};
} FIDVID_STATUS;
typedef union
{
unsigned long long value;
struct
{
unsigned long long /* MSR 0xC001_00[68:64] P-State [4:0] */
CpuFid : 6-0, /* Core Frequency ID. RW: Value <= 2Fh */
CpuDid : 9-6, /* Core Divisor ID. RW: 0h-4h divide by 1-16 */
CpuVid : 16-9, /* Core Voltage ID. RW */
Reserved1 : 22-16,
NbDid : 23-22, /* Northbridge Divisor ID. RW: 0-1 => 0-2 */
Reserved2 : 25-23,
NbVid : 32-25, /* NB VID. RW: MSR 0xC0010071[MaxVid,MinVid]*/
IddValue : 40-32, /* Current Dissipation. RW:00-10b->1,10,100A */
IddDiv : 42-40, /* Current Dissipation Divisor. RW */
Reserved3 : 63-42,
PstateEn : 64-63; /* Pstate enabled. RW */
} Family_10h;
struct
{
unsigned long long /* MSR 0xC001_00[6B:64] P-State [7:0] */
CpuDid : 4-0, /* Core Divisor ID. RW */
CpuFid : 9-4, /* Core Frequency ID. RW */
CpuVid : 16-9, /* Core Voltage ID. RW */
Reserved1 : 32-16,
IddValue : 40-32, /* Current value field. RW */
IddDiv : 42-40, /* Current divisor field. RW */
Reserved2 : 63-42,
PstateEn : 64-63; /* Pstate enabled. RW */
} Family_12h;
struct
{
unsigned long long /* MSR 0xC001_00[6B:64] P-State [7:0] */
CpuDidLSD : 4-0, /* Core Divisor ID least significant digit.RW*/
CpuDidMSD : 9-4, /* Core Divisor ID most significant digit. RW*/
CpuVid : 16-9, /* Core Voltage ID. RW */
Reserved1 : 32-16,
IddValue : 40-32, /* Current value field. RW */
IddDiv : 42-40, /* Current divisor field. RW */
Reserved2 : 63-42,
PstateEn : 64-63; /* Pstate enabled. RW */
} Family_14h;
struct
{
unsigned long long /* MSR 0xC001_00[6B:64] P-state [7:0] */
CpuFid : 6-0, /* Core Frequency ID. RW */
CpuDid : 9-6, /* Core Divisor ID. RW:0h-4h divide by 1-16 */
CpuVid : 16-9, /* Core Voltage ID. RW */
CpuVid_bit : 17-16,
Reserved1 : 22-17,
NbPstate : 23-22, /* Northbrige MSR 0xC001_0071[NbPstateDis] */
Reserved2 : 32-23,
IddValue : 40-32, /* Max Current Dissipation:00-10b->1,10,100A */
IddDiv : 42-40, /* Current Dissipation Divisor. RW */
Reserved3 : 63-42,
PstateEn : 64-63; /* Pstate enabled. RW */
} Family_15h;
struct
{
unsigned long long /* MSR 0xC001_0064 [P-state [7:0]] */
CpuFid : 8-0, /* Core Frequency ID. RW: FFh-10h <Value>*25 */
CpuDfsId : 14-8, /* Core Divisor ID. RW */
CpuVid : 22-14, /* Core Voltage ID. RW */
IddValue : 30-22, /* Current Dissipation in amps. RW */
IddDiv : 32-30, /* Current Dissipation Divisor. RW */
Reserved : 63-32,
PstateEn : 64-63; /* RW: Is this Pstate MSR valid ? */
} Family_17h;
} PSTATEDEF;
typedef union
{
unsigned long long value;
struct
{ /* MSR 0xC001020{0,2,4,6,8,a} ; 0xC001000{0,1,2,3} */
unsigned long long
EventSelect00 : 8-0,
UnitMask : 16-8,
OsUserMode : 18-16,
EdgeDetect : 19-18,
Reserved1 : 20-19,
APIC_Interrupt : 21-20,
Reserved2 : 22-21,
CounterEn : 23-22,
InvCntMask : 24-23,
CntMask : 32-24,
EventSelect08 : 36-32,
Reserved3 : 40-36,
HostGuestOnly : 42-40,
Reserved4 : 64-42;
};
} ZEN_PERF_CTL;
typedef union
{
unsigned long long value;
struct
{
unsigned long long /* MSR 0xC001023{0,2,4,6,8,a} */
EventSelect : 8-0,
UnitMask : 16-8,
Reserved1 : 22-16,
CounterEn : 23-22,
Reserved2 : 42-23,
CoreID : 45-42,
Reserved3 : 46-45,
EnAllSlices : 47-46,
EnAllCores : 48-47,
SliceMask : 52-48,
Reserved4 : 56-52,
ThreadMask : 64-56;
};
} ZEN_L3_PERF_CTL;
#define SMU_AMD_UMC_PERF_CTL_CLK(_umc) (0x00050d00 + (_umc << 20))
typedef union
{
unsigned int value;
struct
{ /* SMU addresses = 0x{0,1,2,3,4,5,6,7}50d00 */
unsigned int
GlblResetMsk : 6-0, /* Six Counters can be reset by GlblReset */
Reserved1 : 24-6,
GlblReset : 25-24,/* Reset Ctr not masked within GlblResetMsk */
GlblMonEn : 26-25,/* Global counter enable */
Reserved2 : 31-26,
CtrClkEn : 32-31;
};
} ZEN_UMC_PERF_CTL_CLK;
#define SMU_AMD_ZEN_UMC_PERF_CTL(_umc, _cha) \
(0x00050d04 + (_umc << 20) + (_cha << 2))
typedef union
{
unsigned int value;
struct
{ /* SMU addresses = 0x{0,1,2,3,4,5,6,7}50d{04,08,0c,10} */
unsigned int
EventSelect : 8-0,
RdWrMask : 10-8, /* Masking: 0=None; 1=Writes; 2=Reads; 3=Rsvd */
PriorityMask : 14-10,/* Masking: 0=Low; 1=Medium; 2=High; 3=Urgent */
ReqSizeMask : 16-14,/* Transactions: 0=None; 1=32B; 2=64B; 3=Rsvd */
ChipSelMask : 20-16,/* Chip Select: 0=CS0; 1=CS1; 2=CS2; 3=CS3 */
ChipIDSel : 24-20,/* Only events from 0=C0; 1=C1; 2=C2; 3=Enable*/
VCSel : 29-24,/* Only events from 0=VC0; 1=VC1; 2=VC2; 3=VC3*/
Reserved : 31-29,
CounterEn : 32-31;
};
} ZEN_UMC_PERF_CTL;
#define SMU_AMD_ZEN_UMC_PERF_CLK_LOW(_cha) \
(0x00050d20 + (_cha << 20))
#define SMU_AMD_ZEN_UMC_PERF_CLK_HIGH(_cha) \
(0x00050d24 + (_cha << 20))
typedef union
{
unsigned long long value;
struct
{
unsigned long long /* MSR 0xC001024{0,2,4,6} */
EventSelect00 : 8-0,
UnitMask : 16-8,
Reserved1 : 22-16,
CounterEn : 23-22,
Reserved2 : 32-23,
EventSelect08 : 36-32,
Reserved3 : 59-36,
EventSelect12 : 61-59,
Reserved4 : 64-61;
};
} ZEN_DF_PERF_CTL;
typedef union
{
unsigned long long value;
struct
{
unsigned long long /* MSR 0xC0010292 */
CurPstateLimit : 3-0, /* CurHwPstateLimit ; BOOST(MAX) */
StartupPstate : 6-3, /* BOOST(MAX) */
DFPstateDis : 7-6,
CurDFVid : 15-7,
MaxCpuCof : 21-15,
MaxDFCof : 26-21,
CpbCap : 29-26,
Reserved1 : 30-29,
MaxCpuCofPlus50 : 31-30, /* RO: Add 50 MHz to Max CPU frequency */
Reserved2 : 32-31,
PC6En : 33-32, /* RW: 0=Disable PC6. 1=Enable PC6 */
Reserved3 : 64-33;
};
} ZEN_PMGT_MISC;
typedef union
{
unsigned long long value;
struct
{
unsigned long long /* Per Core: MSR 0xC0010294 (R/W) */
CC1_TMRSEL : 2-0,
CC1_TMRLEN : 7-2,
HYST_TMRSEL : 9-7,
HYST_TMRLEN : 14-9,
CFOH_TMRLEN : 21-14,
CFOH_TMRSEL : 22-21,
C1E_TMRSEL : 24-22,
C1E_TMRLEN : 29-24,
C1E_EN : 30-29,
Reserved1 : 32-30,
CFSM_DURATION : 39-32,
CFSM_THRESHOLD : 42-39,
CFSM_MISPREDACT : 44-42,
IRM_DECRRATE : 49-44,
IRM_BURSTEN : 52-49,
IRM_THRESHOLD : 56-52,
IRM_MAXDEPTH : 60-56,
CIT_EN : 61-60,
CIT_FASTSAMPLE : 62-61,
CLT_EN : 63-62,
Reserved2 : 64-63;
};
} ZEN_CSTATE_POLICY;
typedef union
{
unsigned long long value;
struct
{
unsigned long long /* Per Core: MSR 0xC0010296 (R/W) */
CCR0_CC1DFSID : 6-0,
CCR0_CC6EN : 7-6,
Reserved1 : 8-7,
CCR1_CC1DFSID : 14-8,
CCR1_CC6EN : 15-14,
Reserved2 : 16-15,
CCR2_CC2DFSID : 22-16,
CCR2_CC6EN : 23-22,
Reserved3 : 32-23,
CCR0_CFOHTMR_LEN: 39-32,
CCR0_CC1E_EN : 40-39,
CCR1_CFOHTMR_LEN: 47-40,
CCR1_CC1E_EN : 48-47,
CCR2_CFOHTMR_LEN: 55-48,
CCR2_CC1E_EN : 56-55,
Reserved4 : 64-56;
};
} ZEN_CSTATE_CONFIG;
typedef union
{
unsigned long long value; /* Per Core: MSR 0xC0010297 (R/0) */
struct
{
unsigned long long
CC6EXIT_DFSID : 6-0,
CC6EXIT_POPUP_EN: 7-6,
CC6CF_DFSID : 13-7,
CC6CF_POPDN_EN : 14-13,
CC6EXIT_STRETCHEN:15-14,
CC6EX_STRCLKDIV2: 16-15, /* CC6EXIT_STRETCHCLKDIV2 */
CC6EX_STRALLDIV2: 17-16, /* CC6EXIT_STRETCHALLDIV2 */
CC6CF_STRETCHEN : 18-17,
CC6CF_STRCLKDIV2: 19-18, /* CC6CF_STRETCHCLKDIV2 */
CC6CF_STRALLDIV2: 20-19, /* CC6CF_STRETCHALLDIV2 */
Reserved : 64-20;
};
struct
{
unsigned long long
CC6CF_PSMID : 14-0,
CC6CF_DSMID : 24-14,
CC6CF_CKS_DSMID : 32-24,
PSTATE_DFSID : 38-32,
PSTATE_POPDN_EN : 39-38,
PSTATE_STRETCHEN: 40-39,
CC6CF_EN : 41-40,
CC6CF_DFSID : 47-41,
CC6CF_STRETCHEN : 48-47,
CC6CF_IVREN : 49-48,
CC6CF_CKS_DSMID2: 51-49,
CC6EXIT_EN : 52-51,
CC6EXIT_DFSID : 58-52,
CC6EXIT_STRETCHEN:59-58,
CC6EXIT_IVREN : 60-59,
CC6EXIT_CKS_DSMID:62-60,
POSTPC6_EN : 63-62,
AUTOSEQCTL_EN : 64-63;
} HWPSTATE;
} ZEN_PMGT_DEFAULT;
typedef union
{
unsigned long long value;
struct
{
unsigned long long /* MSR 0xC0010061 : iff HwPstate == 1 */
CurPstateLimit : 3-0, /* Lowest P-State (highest-performance)*/
Reserved1 : 4-3,
PstateMaxVal : 7-4, /* highest P-State (lowest-performance)*/
Reserved2 : 64-7;
} Family_17h;
} PSTATELIMIT;
typedef union
{
unsigned long long value;
struct
{
unsigned long long /* MSR 0xC0010062 : Family 10h up to 17h */
PstateCmd : 3-0,
Reserved : 64-3;
};
} PSTATECTRL;
typedef union
{
unsigned long long value;
struct
{
unsigned long long /* MSR 0xC0010063 : Family 10h up to 17h */
Current : 3-0,
Reserved : 64-3;
};
} PSTATESTAT;
typedef union
{
unsigned long long value;
struct
{
unsigned long long /* MSR 0xC001_0071 COFVID Status */
CurCpuFid : 6-0,
CurCpuDid : 9-6,
CurCpuVid : 16-9,
CurPstate : 19-16,
Reserved1 : 20-19,
CurCpuVid_bit : 21-20,
Reserved2 : 23-21,
NbPstateDis : 24-23,
CurNbVid : 32-24,
StartupPstate : 35-32,
Reserved3 : 49-35,
MaxCpuCof : 55-49,
Reserved4 : 56-55,
CurPstateLimit : 59-56,
MaxNbCof : 64-59;
} Arch_COF;
struct
{
unsigned long long /* MSR 0xC0010071 COFVID Status */
CurCpuDidLSD : 4-0, /* Current Core Divisor ID. RO */
CurCpuDidMSD : 9-4,
CurCpuVid : 16-9, /* Current Core Voltage ID. RO */
CurPstate : 19-16, /* Current P-state. RO */
Reserved1 : 20-19,
PstateInProgress: 21-20, /* RO: 1=Change, 0=No change */
Reserved2 : 25-21,
CurNbVid : 32-25, /* Current Northbridge VID. RO */
StartupPstate : 35-32, /* Startup P-state Number. RO */
MaxVid : 42-35, /* Maximum Voltage ID. RO */
MinVid : 49-42, /* Minimum Voltage ID. RO */
MainPllOpFidMax : 55-49, /* Main Pll Operating Frequency ID maximum.RO*/
Reserved3 : 56-55,
CurPstateLimit : 59-56, /* Current P-state Limit. RO */
Reserved4 : 64-59;
} Arch_Pll;
} COFVID;
typedef union
{
unsigned long long value;
struct
{
unsigned long long /* Per SMT: MSR 0xC0010073 (RW) */
IOaddr : 16-0, /* 0:dis, [0x1-0xFFF8]+[1...6] Six C-States */
Reserved : 64-16;
};
} CSTATE_BASE_ADDR;
typedef union
{
unsigned long long value; /* MSR 0xC0010055 */
struct
{
unsigned long long
IOMsgAddr : 16-0,
IOMsgData : 24-16,
IntrPndMsgDis : 25-24,
IntrPndMsg : 26-25,
IORd : 27-26,
SmiOnCmpHalt : 28-27, /* SMI on Multi-core halt */
C1eOnCmpHalt : 29-28, /* C1E on Multi-core halt: Fam. 0Fh,10h,11h */
BmStsClrOnHaltEn: 30-29, /* BM_STS clear on Halt enable: Fam. 10h,15h*/
EnPmTmrCheckLoop: 31-30, /* Enable. Fam. 12h,14h,15h_60h-6Fh */
Reserved : 32-31,
RAZ : 64-32; /* [63:29]0Fh, [63:32]10h,11h,15h, [63:0]16h*/
};
} INT_PENDING_MSG;
typedef union
{
unsigned long long value; /* Per SMT: MSR 0xC0010114 (VM_CR) */
struct
{
unsigned long long
DPD : 1-0, /* Debug Port Disable. ReservedBits: F17h */
InterceptInit : 2-1,
DisA20m : 3-2, /* Disable A20 Masking. ReservedBits: F17h */
SVM_Lock : 4-3, /* 0=SvmeDisable is read-write, 1=read-only */
SVME_Disable : 5-4, /* 0 = MSR::EFER[SVME] is RW, 1 = read-only */
Reserved1 : 32-5,
Reserved2 : 64-32;
};
} VM_CR; /* Family: 17h, 16h, 15h, 14h, 12h, 11h, 10h, 0Fh */
typedef union
{
unsigned long long value; /* Per SMT: MSR 0xC0010118 */
struct
{
unsigned long long
SvmLockKey : 64-0; /* Write if (Core::X86::Msr::VM_CR[Lock] == 0)*/
};
} SVM_LOCK_KEY; /* Family: 17h, 16h, 15h, 14h, 12h, 11h, 10h */
typedef union
{
unsigned long long value; /* Pkg: MSR 0xc00102f0 */
struct
{
unsigned long long
LockOut : 1-0, /* R/WO: iff CPUID_Fn80000008_EBX.PPIN */
Enable : 2-1, /* R/W: iff CPUID_Fn80000008_EBX.PPIN */
ReservedBits : 64-2;
};
} AMD_PPIN_CTL; /* Family: 17h, UNK: 16h,15h,14h,12h,11h,10h. Not: 0Fh */
typedef union
{
unsigned long long value; /* Per SMT: MSR 0xc0011020 */
struct
{
unsigned long long
ReservedBits1 : 10-0,
F17h_SSBD_EN : 11-10, /* F17h: 1=Enable SSBD per SMT [low perf] */
ReservedBits2 : 15-11,
CVE_2013_6885 : 16-15, /* F16h erratum 793, CVE-2013-6885 */
ReservedBits3 : 26-16,
HitCurPageOpt : 27-26, /* Disable current table-walk page hit optim.*/
ReservedBits4 : 28-27,
StreamingStore : 29-28, /* F10h...F15h: 1=Disable | Mainboard Enable */
F16h_SSBD : 30-29,
ReservedBits5 : 33-30,
F16h_SSBD_EN : 34-33, /* F16h: 1=Enable SSBD per SMT */
F17h_AgenPick : 35-34, /* Zen 2: Limited Early Redirect Window */
ReservedBits6 : 54-35,
F15h_SSBD : 55-54, /* F15h,F16h,some F17h: disable SpecLockMap */
ReservedBits7 : 64-55;
};
} AMD_LS_CFG;
typedef union
{
unsigned long long value; /* Scope[Core]: MSR 0xc0011021 */
struct
{
unsigned long long
ReservedBits1 : 1-0,
DisIcWayFilter : 5-1, /* F15h-C0: 1=Disable IC way access filter */
HW_IP_Prefetch : 6-5, /* F17h: 1=Disable Instruction Cache */
ReservedBits2 : 9-6,
DisSpecTlbRld : 10-9, /* F16h: 1=Disable speculative ITLB reloads */
ReservedBits3 : 11-10,
DIS_SEQ_PREFETCH: 12-11, /* K8: 1=Disable IC sequential prefetch */
ReservedBits4 : 26-12,
WIDEREAD_PWRSAVE: 27-26, /* F16h: 1=Disable wide read power mgmt */
ReservedBits5 : 39-27,
DisLoopPredictor: 40-39, /* F15h-C0: 1=Disable loop predictor */
ReservedBits6 : 64-40;
};
} AMD_IC_CFG;
typedef union
{
unsigned long long value; /* Scope[Core]: MSR 0xc0011022 */
struct
{
unsigned long long
ReservedBits1 : 4-0,
DisSpecTlbRld : 5-4, /* 1=Disable speculative DTLB reloads */
ReservedBits2 : 8-5,
Dis_WBTOL2 : 9-8, /* F12h: 1=DIS_CLR_WBTOL2_SMC_HIT */
ReservedBits3 : 13-9,
DisHwPf : 14-13,
ReservedBits4 : 15-14,
DisPfHwForSw : 16-15,
L1_HW_Prefetch : 17-16, /* F17h (BIOS) , Disable=1 */
ReservedBits5 : 64-17;
};
} AMD_DC_CFG; /* Family: 12h(BKDG) ... 17h(BIOS) */
typedef union
{
unsigned long long value; /* Scope[Core]: MSR 0xc0011023 */
struct
{
unsigned long long
ReservedBits1 : 49-0,
CombineCr0Cd : 50-49,
ReservedBits5 : 64-50;
};
} AMD_TW_CFG; /* Family: 10h(BKDG) ... 17h */
typedef union
{
unsigned long long value; /* Scope[?]: MSR 0xc0011029 */
struct
{
unsigned long long
ReservedBits1 : 1-0,
LFENCE_SER : 2-1, /* F10h: LFENCE as serializing instruction */
ReservedBits2 : 9-2,
Cross_Proc_Leak : 10-9, /* F17h: CVE-2023-20593 */
ReservedBits3 : 23-10,
CLFLUSH_SER : 24-23, /* F12h: CLFLUSH as serializing instruction */
ReservedBits4 : 64-24;
};
} AMD_DE_CFG; /* Family: 12h ... 17h */
typedef union
{
unsigned long long value; /* SharedC: MSR 0xc001102a */
struct
{
unsigned long long
ReservedBits1 : 35-0,