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Memory Controller data is not available on Intel Gold 6230N #313
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According to Xeon scalable volume 2 , the IMC could be on PCI One way is like function Line 4513 in 6fcba8d
... where any memory controller is scanned on all CPU for a MEMBAR present on PCI Device and PCI Function identifiers But MEMBAR appears NDA! Timings are not specified in vol 2. What do you suggest to experiment and program IMC codes on your hardware ? |
Thanks for your quick reply! emmmmm... I also have no idea right now. |
If you boot an updated kernel we may read more |
I can't boot this image since this server is in the locked server room. |
|
EDIT:
is probably masking the bus Memory BAR is more often remapped from PCI root |
I should run the command
|
Quoting the Scalable/X datasheet volume 2:
This may sound like a tuff part. |
Refreshing the old and unsolved issue #146 My notes:
@wwyf : if you read the kernel debug trace when loading this EDAC driver, you may read the MMIO, next the IMC BAR; strings like:
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Got it, I will give it a try. |
This module is already loaded, and I find the log you want.
This log may correspond to this code. |
sounds like something familiar
|
IMC Timings still not found, but DRAM Power could be improved. This register is not implemented yet in CoreFreq Edit: can you dump its value
Can you pull the ... and also provide the |
Got it. I will have a try. |
Be aware Edit: Issue solved, you can now pull and try latest version. |
The problem is the same as #160, though my CPU is Intel Gold 6230N.
Problems:
corefreq-cli -M
gives no output.This is some output of various commands about environment, may be they are useful.
(
-u
make output too long, so I upload the output as file)corefreq-cli -B -k -u -M.txt
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