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Logic gate & circuit simulation framework; 8-bit CPU simulation.

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daveying/latch

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Latch build & test

This project is called Latch because latch is the most fundamental element of electrical computer, it registers one single bit. the project is aimed to create a logic gate and logic circuit simulation framework, and create a 8-bit CPU simulation based on this framework.

TODO List

  • Gate template
  • Basic gates (NOT, OR, AND, NOR, NAND) base on GateTemplate
  • SR Latch using basic gates
  • Simple scheduler and interface
  • Timer
  • D flip flop using basic gates
  • Change sched::addEvent interface so that useful debug info can be logged when scheduling
    • change Event to include event name and log handle
  • Fix failing test
  • Component template
  • Logger to support loglevel and switch on/off sched logs
    • Loglevel support
    • Schedule log can be redirect to specified file
  • Simulation context
    • Gate factory
    • Fix scheduler singleton issue
    • Fix D flip flop test (Pulse)
    • Two simulation contexts can communicate using wires (UART protocol?)
  • Tool to rendering the gate
    • Option 1: rendering at runtime
    • Option 2: rendering based on logs
  • Fix DelayedNOTGate gate::gate_info<>
  • Fix gate::gate_info<>
  • Name of pins are computed on the fly which saves memory but it's expected to slow down the simulation a lot
    • Schedule log as binary format
    • Tool to plot pin voltage sequence
  • Remove gate namespace
  • Get pin instance using pin name
  • Support floating state, pin connections should be non-directional.
    • Wire class shared by all pins
    • Wire has its own value, inertial or transport delay models can be supported
    • Peers managed by Wire
    • Pin has different interface for component and wire

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Logic gate & circuit simulation framework; 8-bit CPU simulation.

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