JIT SVE: Assertion failed '(targetReg == op1Reg) || (targetReg != op3Reg)' during 'Generate code'

[jakobbotsch]

// Generated by Fuzzlyn v2.3 on 2024-08-23 10:04:52
// Run on Arm64 Windows
// Seed: 12028719405363964033-vectort,vector64,vector128,armsve
// Reduced from 60.4 KiB to 0.7 KiB in 00:00:33
// Hits JIT assert in Release:
// Assertion failed '(targetReg == op1Reg) || (targetReg != op3Reg)' in 'S0:M3():this' during 'Generate code' (IL size 57; hash 0x4541fc9f; FullOpts)
//
//     File: C:\dev\dotnet\runtime2\src\coreclr\jit\hwintrinsiccodegenarm64.cpp Line: 1128
//
using System;
using System.Numerics;
using System.Runtime.Intrinsics;
using System.Runtime.Intrinsics.Arm;

public struct S0
{
    public bool F0;
    public Vector<sbyte> F2;
    public void M3()
    {
        var vr0 = this.F2;
        var vr1 = this.F2;
        var vr2 = this.F2;
        this.F2 = Sve.Splice(vr0, vr1, vr2);
        Program.s_rt.WriteLine(this.F0);
    }
}

public class Program
{
    public static IRuntime s_rt;
    public static void Main()
    {
        new S0().M3();
    }
}

public interface IRuntime
{
    void WriteLine<T>(T value);
}

public class Runtime : IRuntime
{
    public void WriteLine<T>(T value) => System.Console.WriteLine(value);
}

cc @dotnet/arm64-contrib @dotnet/jit-contrib

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[a74nh]

This will also be fixed by #107036.

Should I put this test case into that PR too? And can I mark that PR also fixes this issue?

[jakobbotsch]

Sure, sounds good to do it like that.