xarch: Use ZF and CF flags whenever possible to eliminate test instruction

[kunalspathak]

From "Appendix F Instruction Effects on RFLAGS" of AMD manual and
"Appendix A EFLAGS CROSS-REFERENCE" and "Appendix B EFLAGS CONDITION CODES" of Intel manual, there are many ALU instructions that writes ZF and CF flags. If there is a test instruction that follows such ALU instruction and it operates on same register like ALU, then we could eliminate such test instruction.

I did quick analysis and found handful of places in .NET libraries where we have such pattern and could eliminate it.

For the analysis, I just looked for following pattern:

ALU regX, regY  ; store happens in regX
TEST regX, regX
JE/JNE/JZ/JNZ label

Related discussion : #52297 (comment)

Analysis result: je_jne.txt

[kunalspathak]

@dotnet/jit-contrib

[AndyAyersMS]

Found 903 methods containing 1220 groups

Those are the total number of methods/occurences?

[kunalspathak]

Those are the total number of methods/occurences?

Yes.

[EgorBo]

Same as #6794 ?

[tannergooding]

The first step here is likely updating https://github.com/dotnet/runtime/blob/main/src/coreclr/jit/instrsxarch.h to properly track which instructions modify/read which flags.

Today, we have a flags column and that "roughly" covers which general purpose instructions read or write flags as a whole.

• Noting that this may be incomplete or incorrect and was merely consolidated from two other columns back when I added the flags column for tracking other info: Merging the instrsxarch fp, rf, and wf parameters into a single flags parameter coreclr#19644

We could likely update this to a few helper methods and then a set of flags that track which EFLAGS bits are read/modified. In practice, this would be OF, CF, ZF, SF, and PF as those are the condition codes supported by CMOVcc, Jcc, and SETcc and so we'd use 10 flag bits, which seems reasonable overall and like it wouldn't be overly complex to update/audit.

[tannergooding]

I prototyped correctly tracking the read/written flags: tannergooding@80214bd

Notably, the CMOVcc, SETcc, and Jcc should track just the flag(s) they read, since we have one entry per cc variant; but it should otherwise be correct for both Intel and AMD

[kunalspathak]

I prototyped correctly tracking the read/written flags: tannergooding@80214bd

Notably, the CMOVcc, SETcc, and Jcc should track just the flag(s) they read, since we have one entry per cc variant; but it should otherwise be correct for both Intel and AMD

Thanks @tannergooding. I will try to prototype on top of your changes.

[kunalspathak]

Done by #53214