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Add support for GCC optimized builds in RISCV SiFive u74mc architecture #4641

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Add support for GCC optimized builds in RISCV SiFive u74mc architecture #4641

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9e8864d
Add support for GCC optimized builds in RISCV SiFive u74mc architecture
julianmorillo Sep 16, 2024
db08dd8
Deleted trailing whitespace
julianmorillo Sep 16, 2024
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1 change: 1 addition & 0 deletions easybuild/toolchains/compiler/gcc.py
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Original file line number Diff line number Diff line change
Expand Up @@ -96,6 +96,7 @@ class Gcc(Compiler):
(systemtools.POWER, systemtools.POWER_LE): 'mcpu=native',
(systemtools.X86_64, systemtools.AMD): 'march=native', # implies -mtune=native
(systemtools.X86_64, systemtools.INTEL): 'march=native', # implies -mtune=native
(systemtools.RISCV64, systemtools.SIFIVE): 'march=rv64gc mtune=sifive-7-series', # flags specified in archspec
}
# used with --optarch=GENERIC
COMPILER_GENERIC_OPTION = {
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16 changes: 13 additions & 3 deletions easybuild/tools/systemtools.py
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Expand Up @@ -115,6 +115,7 @@
MOTOROLA = 'Motorola/Freescale'
NVIDIA = 'NVIDIA'
QUALCOMM = 'Qualcomm'
SIFIVE = 'SiFive'

# Family constants
POWER_LE = 'POWER little-endian'
Expand All @@ -133,7 +134,7 @@

CPU_ARCHITECTURES = [AARCH32, AARCH64, POWER, RISCV32, RISCV64, X86_64]
CPU_FAMILIES = [AMD, ARM, INTEL, POWER, POWER_LE, RISCV]
CPU_VENDORS = [AMD, APM, APPLE, ARM, BROADCOM, CAVIUM, DEC, IBM, INTEL, MARVELL, MOTOROLA, NVIDIA, QUALCOMM]
CPU_VENDORS = [AMD, APM, APPLE, ARM, BROADCOM, CAVIUM, DEC, IBM, INTEL, MARVELL, MOTOROLA, NVIDIA, QUALCOMM, SIFIVE]
# ARM implementer IDs (i.e., the hexadeximal keys) taken from ARMv8-A Architecture Reference Manual
# (ARM DDI 0487A.j, Section G6.2.102, Page G6-4493)
VENDOR_IDS = {
Expand All @@ -154,6 +155,8 @@
# IBM POWER9
'8335-GTH': IBM,
'8335-GTX': IBM,
# RISCV
'sifive': SIFIVE,
}
# ARM Cortex part numbers from the corresponding ARM Processor Technical Reference Manuals,
# see http://infocenter.arm.com - Cortex-A series processors, Section "Main ID Register"
Expand Down Expand Up @@ -378,15 +381,15 @@ def get_cpu_vendor():
vendor_regex = re.compile(r"model\s+:\s*((\w|-)+)")
elif arch in [AARCH32, AARCH64]:
vendor_regex = re.compile(r"CPU implementer\s+:\s*(\S+)")

elif arch == RISCV64:
vendor_regex = re.compile(r"uarch\s+:\s*(\S+),\s*")
if vendor_regex and is_readable(PROC_CPUINFO_FP):
vendor_id = None

proc_cpuinfo = read_file(PROC_CPUINFO_FP)
res = vendor_regex.search(proc_cpuinfo)
if res:
vendor_id = res.group(1)

if vendor_id in VENDOR_IDS:
vendor = VENDOR_IDS[vendor_id]
_log.debug("Determined CPU vendor on Linux as being '%s' via regex '%s' in %s",
Expand Down Expand Up @@ -493,6 +496,13 @@ def get_cpu_model():
model = vendor + ' ' + ' + '.join(id_list)
_log.debug("Determined CPU model on Linux using regex '%s' in %s: %s",
model_regex.pattern, PROC_CPUINFO_FP, model)
elif arch == RISCV64:
model_regex = re.compile(r"uarch\s+:\s*(\S+)\s*")
res = model_regex.search(proc_cpuinfo)
if res is not None:
model = res.group(1)
_log.debug("Determined CPU model on Linux using regex '%s' in %s: %s",
model_regex.pattern, PROC_CPUINFO_FP, model)
else:
# we need 'model name' on Linux/x86, but 'model' is there first with different info
# 'model name' is not there for Linux/POWER, but 'model' has the right info
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