- Circuit: 12-bit unsigned adders
- Selection criteria: pareto optimal sub-set wrt. MED [%] and Latency parameters
| Circuit name | MAE% | WCE% | EP% | MRE% | MSE | PowerW | Delayns | LUTs | Download |
|---|---|---|---|---|---|---|---|---|---|
| add12u_0FT | 0.0024 | 0.049 | 6.25 | 0.0085 | 1.0 | 0.44 | 9.1 | 16 | [Verilog] [VerilogPDK45] [C] |
| add12u_1DL | 0.0061 | 0.012 | 50.00 | 0.017 | 0.5 | 0.44 | 8.0 | 15 | [Verilog] [VerilogPDK45] [C] |
| add12u_1C0 | 0.0098 | 0.024 | 62.50 | 0.026 | 1.0 | 0.43 | 7.7 | 17 | [Verilog] [VerilogPDK45] [C] |
| add12u_3AF | 0.072 | 0.23 | 94.73 | 0.20 | 53 | 0.38 | 7.2 | 12 | [Verilog] [VerilogPDK45] [C] |
| add12u_013 | 0.21 | 0.82 | 97.84 | 0.58 | 474 | 0.33 | 7.0 | 7.0 | [Verilog] [VerilogPDK45] [C] |
| add12u_0G2 | 0.48 | 1.59 | 99.23 | 1.31 | 2316 | 0.32 | 6.6 | 6.0 | [Verilog] [VerilogPDK45] [C] |
| add12u_007 | 1.83 | 5.98 | 99.80 | 5.13 | 32903 | 0.31 | 6.5 | 4.0 | [Verilog] [VerilogPDK45] [C] |
| add12u_0MC | 3.12 | 6.25 | 100.00 | 8.37 | 85092 | 0.29 | 6.1 | 2.0 | [Verilog] [VerilogPDK45] [C] |
| add12u_1JB | 12.50 | 25.00 | 100.00 | 30.48 | 13286.96e2 | 0.27 | 5.1 | 0 | [Verilog] [VerilogPDK45] [C] |
PRABAKARAN B. S., MRAZEK V., VASICEK Z., SEKANINA L., SHAFIQUE M. ApproxFPGAs: Embracing ASIC-based Approximate Arithmetic Components for FPGA-Based Systems. DAC 2020.