crp42602y_measure_pulse.pio

.program crp42602y_measure_pulse

timeout:
    in null, 32       [0]  ; 0 indicates timeout
    irq wait 0 rel    [0]  ; relative IRQ allows to distinguish state machine in IRQ handler (IRQ0 0 ~ 3 for sm 0 ~ 3), wait until clear

public entry_point:
.wrap_target
    out y, 32         [0]  ; update timeout value
    mov x, !null      [0]  ; set 0xFFFFFFFF to x 
                           ; (5 cycles from 0->1 edge to here)
term1:                     ; to count 1-term by 1/4 clock
    jmp pin term1_1   [0]
    jmp term1_end     [0]
term1_1:
    jmp x!=y term1_2  [0]  ; check timeout
    jmp timeout       [0]
term1_2:
    jmp x-- term1     [1]  ; count div by 4 cycles
    jmp timeout       [0]
term1_end:
    in x, 32          [0]  ; send term1 counts
    mov x, !null      [0]  ; set 0xFFFFFFFF to x
                           ; (4 cycles from 1->0 edge to here)
term0:                     ; to count 0-term by 1/4 clock
    jmp pin term0_end [0]
    jmp x!=y term0_1  [0]  ; check timeout
    jmp timeout       [0]
term0_1:
    jmp x-- term0     [1]  ; count div by 4 cycles
    jmp timeout       [0]
term0_end:
    in x, 32          [0]  ; send term0 counts
    irq 0 rel         [0]  ; relative IRQ allows to distinguish state machine in IRQ handler (IRQ0 0 ~ 3 for sm 0 ~ 3)
.wrap

; ==============================================================================================
% c-sdk {

static inline void crp42602y_measure_pulse_program_init(PIO pio, uint sm, uint offset, uint entry_point, pio_sm_config (*get_default_config)(uint), uint pin)
{
    pio_sm_set_consecutive_pindirs(pio, sm, pin, 1, false);

    pio_sm_config sm_config = (*get_default_config)(offset);

    sm_config_set_clkdiv(&sm_config, 125);  // divide to 1MHz
    sm_config_set_jmp_pin(&sm_config, pin);
    sm_config_set_in_pins(&sm_config, pin); // PINCTRL_IN_BASE for wait
    sm_config_set_out_shift(&sm_config, false, true, 32);  // shift_left, autopull, 32bit
    sm_config_set_in_shift(&sm_config, false, true, 32);  // shift_left, autopush, 32bit

    pio_sm_init(pio, sm, offset, &sm_config);
    pio_sm_set_pins(pio, sm, 0); // clear pins

    pio_sm_set_enabled(pio, sm, false);
    pio_sm_clear_fifos(pio, sm);
    pio_sm_drain_tx_fifo(pio, sm);
    pio_sm_set_enabled(pio, sm, true);

    pio_sm_exec(pio, sm, pio_encode_jmp(offset + entry_point));
}

%}