phy: move Restart/Status and change rx_init_restart/reset behaviour (…

…required on Artix7).
enjoy-digital · Oct 30, 2020 · 0da85d8 · 0da85d8
1 parent 46dc6f8
commit 0da85d8
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Showing 2 changed files with 11 additions and 9 deletions.
diff --git a/litesata/phy/__init__.py b/litesata/phy/__init__.py
@@ -56,17 +56,10 @@ def __init__(self, device, pads, gen, clk_freq, refclk=None, data_width=16):
             self.submodules.crg = A7LiteSATAPHYCRG(refclk, pads, self.phy, gen)
         else:
             raise NotImplementedError
-        self.comb += [
-            self.phy.tx_init.restart.eq(~self.enable.storage),
-            self.phy.rx_init.restart.eq(~self.enable.storage),
-            self.status.fields.tx_ready.eq(self.phy.tx_init.done),
-            self.status.fields.rx_ready.eq(self.phy.rx_init.done),
-        ]
 
         # Control
         self.submodules.ctrl = LiteSATAPHYCtrl(self.phy, self.crg, clk_freq)
-        self.comb += self.status.fields.ctrl_ready.eq(self.ctrl.ready)
-        self.comb += self.status.fields.ready.eq(self.phy.ready & self.ctrl.ready)
+
 
         # Datapath
         self.submodules.datapath = LiteSATAPHYDatapath(self.phy, self.ctrl)
@@ -75,3 +68,13 @@ def __init__(self, device, pads, gen, clk_freq, refclk=None, data_width=16):
             self.ctrl.misalign.eq(self.datapath.misalign)
         ]
         self.sink, self.source = self.datapath.sink, self.datapath.source
+
+        # Restart/Status
+        self.comb += [
+            self.phy.tx_init.restart.eq(~self.enable.storage),
+            self.phy.rx_init.restart.eq(~self.enable.storage | self.ctrl.rx_reset),
+            self.status.fields.ctrl_ready.eq(self.ctrl.ready),
+            self.status.fields.ready.eq(self.phy.ready & self.ctrl.ready),
+            self.status.fields.tx_ready.eq(self.phy.tx_init.done),
+            self.status.fields.rx_ready.eq(self.phy.rx_init.done),
+        ]
diff --git a/litesata/phy/ctrl.py b/litesata/phy/ctrl.py
@@ -130,7 +130,6 @@ def __init__(self, trx, crg, clk_freq):
             align_timer.wait.eq(1),
             If(~trx.rx_idle,
                 If(sink.valid & (self.sink.charisk == 0b0001) & (self.sink.data == primitives["ALIGN"]),
-                    self.rx_reset.eq(1),
                     NextState("SEND-ALIGN")
                 )
             )