README: update.

enjoy-digital · Nov 20, 2020 · 9fc1279 · 9fc1279
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diff --git a/README.md b/README.md
@@ -34,9 +34,11 @@ design flow by generating the verilog rtl that you will use as a standard core.
 PHY:
   - Xilinx 7-Series (Kintex7, Artix7)
   - Xilinx Ultrascale
+  - Xilinx Ultrascale+
   - OOB, COMWAKE, COMINIT
   - ALIGN inserter/remover and bytes alignment on K28.5
   - 8B/10B encoding/decoding in transceiver
+  - Automatic TX/RX P/N polarity detection and swap.
   - Errors detection and reporting
   - 32 bits interface
   - 1.5/3.0/6.0GBps supported speeds (respectively 37.5/75/150MHz system clk)