phy/a7/s7sataphy: expose tx_buffer_enable/rx_buffer_enable.

enjoy-digital · Oct 30, 2020 · a10d497 · a10d497
1 parent 0da85d8
commit a10d497
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Showing 2 changed files with 6 additions and 10 deletions.
diff --git a/litesata/phy/a7sataphy.py b/litesata/phy/a7sataphy.py
@@ -77,7 +77,7 @@ def __init__(self, refclk, pads, gtp, gen):
 # --------------------------------------------------------------------------------------------------
 
 class A7LiteSATAPHY(Module):
-    def __init__(self, pads, gen, clk_freq, data_width=16):
+    def __init__(self, pads, gen, clk_freq, data_width=16, tx_buffer_enable=False, rx_buffer_enable=False):
         assert data_width in [16, 32]
         # Common signals
         self.data_width     = data_width
@@ -164,11 +164,11 @@ def __init__(self, pads, gen, clk_freq, data_width=16):
         rxcdr_cfg = cdr_config[gen]
 
         # TX Init ----------------------------------------------------------------------------------
-        self.submodules.tx_init = tx_init = GTPTXInit(clk_freq, buffer_enable=False)
+        self.submodules.tx_init = tx_init = GTPTXInit(clk_freq, buffer_enable=tx_buffer_enable)
         self.comb += tx_init.plllock.eq(self.qplllock)
 
         # RX Init ----------------------------------------------------------------------------------
-        self.submodules.rx_init = rx_init = GTPRXInit(clk_freq, buffer_enable=False)
+        self.submodules.rx_init = rx_init = GTPRXInit(clk_freq, buffer_enable=rx_buffer_enable)
         self.comb += rx_init.plllock.eq(self.qplllock)
 
         # Ready ------------------------------------------------------------------------------------
@@ -252,8 +252,6 @@ def __init__(self, pads, gen, clk_freq, data_width=16):
 
         # GTPE2_CHANNEL Instance -------------------------------------------------------------------
         class Open(Signal): pass
-        tx_buffer_enable = False
-        rx_buffer_enable = False
         rxphaligndone = Signal()
         gtp_params = dict(
             # Simulation-Only Attributes

diff --git a/litesata/phy/k7sataphy.py b/litesata/phy/k7sataphy.py
@@ -78,7 +78,7 @@ def __init__(self, refclk, pads, gtx, gen):
 # --------------------------------------------------------------------------------------------------
 
 class K7LiteSATAPHY(Module):
-    def __init__(self, pads, gen, clk_freq, data_width=16):
+    def __init__(self, pads, gen, clk_freq, data_width=16, tx_buffer_enable=False, rx_buffer_enable=False):
         assert data_width in [16, 32]
         # Common signals
         self.data_width     = data_width
@@ -165,11 +165,11 @@ def __init__(self, pads, gen, clk_freq, data_width=16):
         rxcdr_cfg = cdr_config[gen]
 
         # TX Init ----------------------------------------------------------------------------------
-        self.submodules.tx_init = tx_init = GTXTXInit(clk_freq, buffer_enable=False)
+        self.submodules.tx_init = tx_init = GTXTXInit(clk_freq, buffer_enable=tx_buffer_enable)
         self.comb += tx_init.plllock.eq(self.cplllock)
 
         # RX Init ----------------------------------------------------------------------------------
-        self.submodules.rx_init = rx_init = GTXRXInit(clk_freq, buffer_enable=False)
+        self.submodules.rx_init = rx_init = GTXRXInit(clk_freq, buffer_enable=rx_buffer_enable)
         self.comb += rx_init.plllock.eq(self.cplllock)
 
         # Ready ------------------------------------------------------------------------------------
@@ -247,8 +247,6 @@ def __init__(self, pads, gen, clk_freq, data_width=16):
 
         # GTXE2_CHANNEL Instance -------------------------------------------------------------------
         class Open(Signal): pass
-        tx_buffer_enable = False
-        rx_buffer_enable = False
         gtx_params = dict(
             # Simulation-Only Attributes
             p_SIM_RECEIVER_DETECT_PASS     = "TRUE",