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software/Dump: add add_scope_clk and add_scope_trig methods and add s…
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…cope_clk/trig to dumps.
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enjoy-digital committed Sep 3, 2020
1 parent 219a901 commit 69de7c4
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Showing 2 changed files with 15 additions and 6 deletions.
11 changes: 9 additions & 2 deletions litescope/software/driver/analyzer.py
Original file line number Diff line number Diff line change
Expand Up @@ -32,7 +32,10 @@ def __init__(self, regs, name, config_csv=None, debug=False):
self.group = 0
self.data = DumpData(self.data_width)

# disable trigger and storage
self.offset = 0
self.length = None

# Disable trigger and storage
self.trigger_enable.write(0)
self.storage_enable.write(0)

Expand Down Expand Up @@ -104,6 +107,8 @@ def run(self, offset=0, length=None):
length = self.depth
assert offset < self.depth
assert length <= self.depth
self.offset = offset
self.length = length
if self.debug:
print("[running]...")
self.storage_offset.write(offset)
Expand All @@ -124,7 +129,7 @@ def upload(self):
length = self.storage_length.read()
for position in range(1, length + 1):
if self.debug:
sys.stdout.write("|{}>{}| {}%\r".format('=' * (20*position//length),
sys.stdout.write("[{}>{}] {}%\r".format('=' * (20*position//length),
' ' * (20-20*position//length),
100*position//length))
sys.stdout.flush()
Expand Down Expand Up @@ -153,6 +158,8 @@ def save(self, filename, samplerate=None, flatten=False):
dump.add_from_layout(self.layouts[self.group], self.data)
else:
dump.add_from_layout_flatten(self.layouts[self.group], self.data)
dump.add_scope_clk()
dump.add_scope_trig(self.offset)
dump.write(filename)

def get_instant_value(self, group, name):
Expand Down
10 changes: 6 additions & 4 deletions litescope/software/dump/common.py
Original file line number Diff line number Diff line change
Expand Up @@ -77,22 +77,24 @@ def add_from_layout(self, layout, variable):
values2x = [values[i//2] for i in range(len(values)*2)]
self.add(DumpVariable(name, sample_width, values2x))
offset += sample_width
self.add(DumpVariable("scope_clk", 1, [1, 0]*(len(self)//2)))

def add_from_layout_flatten(self, layout, variable):
offset = 0
for name, sample_width in layout:
# The samples from the logic analyzer end up in an array of size sample size
# and have n (number of channel) bits. The following does a bit slice on the array
# elements (implemented above)
values = variable[offset:offset+sample_width]
values = variable[offset:offset+sample_width]
values_flatten = [values[i//sample_width] >> (i % sample_width ) & 1 for i in range(len(values)*sample_width)]
self.add(DumpVariable(name, 1, values_flatten))
offset += sample_width
# the clock.. might need some more love here. the clock pattern probably should be sample_width wide
# e.g. 11110000 and not 10101010

def add_scope_clk(self):
self.add(DumpVariable("scope_clk", 1, [1, 0]*(len(self)//2)))

def add_scope_trig(self, offset):
self.add(DumpVariable("scope_trig", 1, [0]*offset + [1]*(len(self)-offset)))

def __len__(self):
l = 0
for variable in self.variables:
Expand Down

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