integration/soc/add_uart: add Model/Sim.

enjoy-digital · Mar 25, 2020 · 09a3ce0 · 09a3ce0
1 parent 3f43c6a
commit 09a3ce0
Showing 1 changed file with 7 additions and 0 deletions.
diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py
@@ -931,6 +931,13 @@ def add_uart(self, name, baudrate=115200, fifo_depth=16):
         elif name in ["crossover"]:
             self.submodules.uart = uart.UARTCrossover()
 
+        # Model/Sim
+        elif name in ["model", "sim"]:
+            self.submodules.uart_phy = uart.RS232PHYModel(self.platform.request("serial"))
+            self.submodules.uart = ResetInserter()(uart.UART(self.uart_phy,
+                tx_fifo_depth = fifo_depth,
+                rx_fifo_depth = fifo_depth))
+
         # JTAG Atlantic
         elif name in ["jtag_atlantic"]:
             from litex.soc.cores.jtag import JTAGAtlantic