From 16008d3f3a493b081bd25c97fc1f2d64b55016c4 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 4 Jan 2021 14:40:49 +0100 Subject: [PATCH] cpu/vexriscv/cpu-count: fix type and add comment (thanks dayjaby). --- litex/soc/cores/cpu/vexriscv_smp/core.py | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/litex/soc/cores/cpu/vexriscv_smp/core.py b/litex/soc/cores/cpu/vexriscv_smp/core.py index aacdad69fd..666100f533 100644 --- a/litex/soc/cores/cpu/vexriscv_smp/core.py +++ b/litex/soc/cores/cpu/vexriscv_smp/core.py @@ -8,9 +8,10 @@ import os from os import path -from litex import get_data_mod from migen import * +from litex import get_data_mod + from litex.soc.interconnect import wishbone from litex.soc.interconnect.csr import * from litex.soc.cores.cpu import CPU, CPU_GCC_TRIPLE_RISCV32 @@ -49,7 +50,7 @@ class VexRiscvSMP(CPU): @staticmethod def args_fill(parser): - parser.add_argument("--cpu-count", default=1, help="") + parser.add_argument("--cpu-count", default=1, help="Number of CPU(s) in the cluster.", type=int) parser.add_argument("--with-coherent-dma", action='store_true', help="Enable Coherent DMA Slave interface.") parser.add_argument("--without-coherent-dma", action='store_true', help="Disable Coherent DMA Slave interface.") parser.add_argument("--dcache-width", default=None, help="L1 data cache bus width.")