Merge pull request #447 from antmicro/spi-xip

Add initial support for the new LiteSPI core

litex/boards/platforms/netv2.py

@@ -23,7 +23,7 @@
         Subsignal("cs_n", Pins("T19")),
         Subsignal("mosi", Pins("P22")),
         Subsignal("miso", Pins("R22")),
-        Subsignal("vpp", Pins("P21")),
+        Subsignal("wp",   Pins("P21")),
         Subsignal("hold", Pins("R21")),
         IOStandard("LVCMOS33")
     ),

litex/boards/targets/netv2.py

@@ -13,12 +13,16 @@
 from litex.soc.integration.soc_core import *
 from litex.soc.integration.soc_sdram import *
 from litex.soc.integration.builder import *
+from litex.soc.integration.soc import *
 
 from litedram.modules import K4B2G1646F
 from litedram.phy import s7ddrphy
 
 from liteeth.phy.rmii import LiteEthPHYRMII
 
+from litespi import LiteSPI
+from litespi.phy.generic import LiteSPIPHY
+
 # CRG ----------------------------------------------------------------------------------------------
 
 class _CRG(Module):
@@ -46,7 +50,7 @@ def __init__(self, platform, sys_clk_freq):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    def __init__(self, sys_clk_freq=int(100e6), with_ethernet=False, **kwargs):
+    def __init__(self, sys_clk_freq=int(100e6), with_ethernet=False, with_spi_xip=False, **kwargs):
         platform = netv2.Platform()
 
         # SoCCore ----------------------------------------------------------------------------------
@@ -72,6 +76,14 @@ def __init__(self, sys_clk_freq=int(100e6), with_ethernet=False, **kwargs):
                 l2_cache_reverse        = True
             )
 
+        # SPI XIP ----------------------------------------------------------------------------------
+        if with_spi_xip:
+            spi_xip_size = 1024*1024*8
+            self.submodules.spiphy = LiteSPIPHY(platform.request("spiflash4x"))
+            self.submodules.spictl = LiteSPI(phy=self.spiphy, endianness=self.cpu.endianness)
+            spi_xip_region = SoCRegion(origin=self.mem_map.get("spixip", None), size=spi_xip_size, cached=False)
+            self.bus.add_slave(name="spixip", slave=self.spictl.bus, region=spi_xip_region)
+
         # Ethernet ---------------------------------------------------------------------------------
         if with_ethernet:
             self.submodules.ethphy = LiteEthPHYRMII(
@@ -88,9 +100,11 @@ def main():
     soc_sdram_args(parser)
     parser.add_argument("--with-ethernet", action="store_true",
                         help="enable Ethernet support")
+    parser.add_argument("--with-spi-xip", action="store_true",
+                        help="enable SPI XIP support")
     args = parser.parse_args()
 
-    soc = BaseSoC(with_ethernet=args.with_ethernet, **soc_sdram_argdict(args))
+    soc = BaseSoC(with_ethernet=args.with_ethernet, with_spi_xip=args.with_spi_xip, **soc_sdram_argdict(args))
     builder = Builder(soc, **builder_argdict(args))
     builder.build()
 

litex/tools/litex_sim.py

@@ -16,6 +16,10 @@
 from litex.soc.integration.common import *
 from litex.soc.integration.soc_sdram import *
 from litex.soc.integration.builder import *
+from litex.soc.integration.soc import *
+
+from litespi import LiteSPI
+from litespi.phy.model import LiteSPIPHYModel
 
 from litedram import modules as litedram_modules
 from litedram.common import *
@@ -156,6 +160,7 @@ class SimSoC(SoCSDRAM):
 
     def __init__(self,
         with_sdram            = False,
+        with_spi_xip          = False,
         with_ethernet         = False,
         with_etherbone        = False,
         etherbone_mac_address = 0x10e2d5000001,
@@ -177,6 +182,14 @@ def __init__(self,
         # CRG --------------------------------------------------------------------------------------
         self.submodules.crg = CRG(platform.request("sys_clk"))
 
+        # SPI XIP ----------------------------------------------------------------------------------
+        if with_spi_xip:
+            spi_xip_size = kwargs["spi_xip_size"]
+            self.submodules.spiphy = LiteSPIPHYModel(spi_xip_size, init=kwargs["spi_xip_init"])
+            self.submodules.spictl = LiteSPI(phy=self.spiphy, endianness=self.cpu.endianness)
+            spi_xip_region = SoCRegion(origin=self.mem_map.get("spixip", None), size=spi_xip_size, cached=False)
+            self.bus.add_slave(name="spixip", slave=self.spictl.bus, region=spi_xip_region)
+
         # SDRAM ------------------------------------------------------------------------------------
         if with_sdram:
             sdram_clk_freq   = int(100e6) # FIXME: use 100MHz timings
@@ -279,6 +292,8 @@ def main():
     parser.add_argument("--threads",              default=1,               help="Set number of threads (default=1)")
     parser.add_argument("--rom-init",             default=None,            help="rom_init file")
     parser.add_argument("--ram-init",             default=None,            help="ram_init file")
+    parser.add_argument("--with-spi-xip",         action="store_true",     help="Enable SPI XIP support")
+    parser.add_argument("--spi-xip-init",         default=None,            help="spi_xip_init file")
     parser.add_argument("--with-sdram",           action="store_true",     help="Enable SDRAM support")
     parser.add_argument("--sdram-module",         default="MT48LC16M16",   help="Select SDRAM chip")
     parser.add_argument("--sdram-data-width",     default=32,              help="Set SDRAM chip data width")
@@ -311,6 +326,9 @@ def main():
     soc_kwargs["uart_name"] = "sim"
     if args.rom_init:
         soc_kwargs["integrated_rom_init"] = get_mem_data(args.rom_init, cpu_endianness)
+    if args.with_spi_xip:
+        soc_kwargs["spi_xip_size"] = 8*1024*1024
+        soc_kwargs["spi_xip_init"] = get_mem_data(args.spi_xip_init, "big") if args.spi_xip_init is not None else None
     if not args.with_sdram:
         soc_kwargs["integrated_main_ram_size"] = 0x10000000 # 256 MB
         if args.ram_init is not None:
@@ -328,6 +346,7 @@ def main():
     # SoC ------------------------------------------------------------------------------------------
     soc = SimSoC(
         with_sdram     = args.with_sdram,
+        with_spi_xip   = args.with_spi_xip,
         with_ethernet  = args.with_ethernet,
         with_etherbone = args.with_etherbone,
         with_analyzer  = args.with_analyzer,

litex_setup.py

@@ -25,6 +25,7 @@
     ("litevideo",    ("https://github.com/enjoy-digital/", False, True)),
     ("litescope",    ("https://github.com/enjoy-digital/", False, True)),
     ("litejesd204b", ("https://github.com/enjoy-digital/", False, True)),
+    ("litespi",      ("https://github.com/litex-hub/",     False, True)),
 
     # LiteX boards support
     ("litex-boards",   ("https://github.com/litex-hub/", False, True)),