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soc/cores/uart: use reset_less on accumulator, reg, bitcount to reduce.
This reduces logic a bit. It does not make large difference on usual design with only 1 UART, but is interesting on designs with hundreds of UARTs used to "document" FPGA boards :) (similar to https://github.com/enjoy-digital/camlink_4k/blob/master/ios_stream.py)
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