diff --git a/components/bootloader/Kconfig.projbuild b/components/bootloader/Kconfig.projbuild
index a45fcd4a750..895085d383b 100644
--- a/components/bootloader/Kconfig.projbuild
+++ b/components/bootloader/Kconfig.projbuild
@@ -428,17 +428,22 @@ menu "Security features"
         select MBEDTLS_ECDSA_C
         depends on SECURE_SIGNED_ON_BOOT || SECURE_SIGNED_ON_UPDATE
 
+    config SECURE_ESP32_SUPPORTS_RSA
+        bool
+        default y if ESP32_REV_MIN_FULL >= 300
+        depends on IDF_TARGET_ESP32
+
     config SECURE_BOOT_SUPPORTS_RSA
         bool
         default y
-        depends on ESP32_REV_MIN_3 || IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32C3 || IDF_TARGET_ESP32S3
+        # RSA secure boot is supported in ESP32 revision >= v3.0
+        depends on SECURE_ESP32_SUPPORTS_RSA || IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32C3 || IDF_TARGET_ESP32S3 # NOERROR
 
     config SECURE_TARGET_HAS_SECURE_ROM_DL_MODE
         bool
         default y
         depends on IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32C3 || IDF_TARGET_ESP32S3
 
-
     config SECURE_SIGNED_APPS_NO_SECURE_BOOT
         bool "Require signed app images"
         depends on !SECURE_BOOT
@@ -508,7 +513,8 @@ menu "Security features"
     config SECURE_BOOT
         bool "Enable hardware Secure Boot in bootloader (READ DOCS FIRST)"
         default n
-        depends on IDF_TARGET_ESP32 || IDF_TARGET_ESP32S2 || ESP32C3_REV_MIN >= 3 || IDF_TARGET_ESP32S3
+        # Secure boot is not supported for ESP32-C3 revision < v0.3
+        depends on IDF_TARGET_ESP32 || IDF_TARGET_ESP32S2 || (IDF_TARGET_ESP32C3 && ESP32C3_REV_MIN_FULL >= 3) || IDF_TARGET_ESP32S3 # NOERROR
         select ESPTOOLPY_NO_STUB if !IDF_TARGET_ESP32 && !IDF_TARGET_ESP32S2
         help
             Build a bootloader which enables Secure Boot on first boot.
@@ -521,7 +527,7 @@ menu "Security features"
 
     choice SECURE_BOOT_VERSION
         bool "Select secure boot version"
-        default SECURE_BOOT_V2_ENABLED if ESP32_REV_MIN_3
+        default SECURE_BOOT_V2_ENABLED if ESP32_REV_MIN_FULL >= 300
         depends on SECURE_BOOT
         help
             Select the Secure Boot Version. Depends on the Chip Revision.
@@ -874,7 +880,7 @@ menu "Security features"
         default SECURE_ENABLE_SECURE_ROM_DL_MODE if SECURE_TARGET_HAS_SECURE_ROM_DL_MODE && !SECURE_FLASH_ENCRYPTION_MODE_DEVELOPMENT # NOERROR
         default SECURE_INSECURE_ALLOW_DL_MODE
         depends on SECURE_BOOT_V2_ENABLED || SECURE_FLASH_ENC_ENABLED
-        depends on !IDF_TARGET_ESP32 || ESP32_REV_MIN_3
+        depends on !(IDF_TARGET_ESP32 && ESP32_REV_MIN_FULL < 300)
 
         config SECURE_DISABLE_ROM_DL_MODE
             bool "UART ROM download mode (Permanently disabled (recommended))"
diff --git a/components/bootloader/subproject/main/component.mk b/components/bootloader/subproject/main/component.mk
index c41e8b70958..87e95520aeb 100644
--- a/components/bootloader/subproject/main/component.mk
+++ b/components/bootloader/subproject/main/component.mk
@@ -17,7 +17,7 @@ ifdef CONFIG_IDF_TARGET_ESP32
     ifndef CONFIG_SPI_FLASH_ROM_DRIVER_PATCH
         LINKER_SCRIPTS += $(IDF_PATH)/components/esp_rom/$(IDF_TARGET)/ld/$(IDF_TARGET).rom.spiflash.ld
     endif
-    ifdef CONFIG_ESP32_REV_MIN_3
+    ifeq ($(shell expr $(CONFIG_ESP32_REV_MIN_FULL) \>= 300), 1)
         LINKER_SCRIPTS += $(IDF_PATH)/components/esp_rom/$(IDF_TARGET)/ld/$(IDF_TARGET).rom.eco3.ld
     endif
 endif
diff --git a/components/bootloader_support/include/esp_app_format.h b/components/bootloader_support/include/esp_app_format.h
index 1f547d3bfbf..11fba02d912 100644
--- a/components/bootloader_support/include/esp_app_format.h
+++ b/components/bootloader_support/include/esp_app_format.h
@@ -79,8 +79,15 @@ typedef struct {
                                 * pin and sets this field to 0xEE=disabled) */
     uint8_t spi_pin_drv[3];     /*!< Drive settings for the SPI flash pins (read by ROM bootloader) */
     esp_chip_id_t chip_id;      /*!< Chip identification number */
-    uint8_t min_chip_rev;       /*!< Minimum chip revision supported by image */
-    uint8_t reserved[8];       /*!< Reserved bytes in additional header space, currently unused */
+    uint8_t min_chip_rev;       /*!< Minimal chip revision supported by image
+                                 * After the Major and Minor revision eFuses were introduced into the chips, this field is no longer used.
+                                 * But for compatibility reasons, we keep this field and the data in it.
+                                 * Use min_chip_rev_full instead.
+                                 * The software interprets this as a Major version for most of the chips and as a Minor version for the ESP32-C3.
+                                 */
+    uint16_t min_chip_rev_full; /*!< Minimal chip revision supported by image, in format: major * 100 + minor */
+    uint16_t max_chip_rev_full; /*!< Maximal chip revision supported by image, in format: major * 100 + minor */
+    uint8_t reserved[4];        /*!< Reserved bytes in additional header space, currently unused */
     uint8_t hash_appended;      /*!< If 1, a SHA256 digest "simple hash" (of the entire image) is appended after the checksum.
                                  * Included in image length. This digest
                                  * is separate to secure boot and only used for detecting corruption.
diff --git a/components/bootloader_support/include/esp_secure_boot.h b/components/bootloader_support/include/esp_secure_boot.h
index 9bb8dfec0b7..42e8d1365c5 100644
--- a/components/bootloader_support/include/esp_secure_boot.h
+++ b/components/bootloader_support/include/esp_secure_boot.h
@@ -200,7 +200,7 @@ typedef struct {
  */
 esp_err_t esp_secure_boot_verify_ecdsa_signature_block(const esp_secure_boot_sig_block_t *sig_block, const uint8_t *image_digest, uint8_t *verified_digest);
 
-#if !CONFIG_IDF_TARGET_ESP32 || CONFIG_ESP32_REV_MIN_3
+#if !CONFIG_IDF_TARGET_ESP32 || CONFIG_ESP32_REV_MIN_FULL >= 300
 /**
  * @brief Structure to hold public key digests calculated from the signature blocks of a single image.
  *
@@ -223,7 +223,7 @@ typedef struct {
  *
  */
 esp_err_t esp_secure_boot_verify_rsa_signature_block(const ets_secure_boot_signature_t *sig_block, const uint8_t *image_digest, uint8_t *verified_digest);
-#endif // !CONFIG_IDF_TARGET_ESP32 || CONFIG_ESP32_REV_MIN_3
+#endif // !CONFIG_IDF_TARGET_ESP32 || CONFIG_ESP32_REV_MIN_FULL >= 300
 
 /** @brief Legacy ECDSA verification function
  *
diff --git a/components/bootloader_support/src/bootloader_clock_init.c b/components/bootloader_support/src/bootloader_clock_init.c
index 97c7b9f7f54..a08aa50dc4a 100644
--- a/components/bootloader_support/src/bootloader_clock_init.c
+++ b/components/bootloader_support/src/bootloader_clock_init.c
@@ -7,6 +7,7 @@
 #include "soc/soc.h"
 #include "soc/rtc.h"
 #include "soc/efuse_periph.h"
+#include "soc/chip_revision.h"
 #include "soc/rtc_cntl_reg.h"
 #if CONFIG_IDF_TARGET_ESP32
 #include "soc/dport_reg.h"
@@ -33,7 +34,7 @@ __attribute__((weak)) void bootloader_clock_configure(void)
      * document). For rev. 0, switch to 240 instead if it has been enabled
      * previously.
      */
-    if (efuse_hal_get_major_chip_version() == 0 &&
+    if (!ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 100) &&
             DPORT_REG_GET_FIELD(DPORT_CPU_PER_CONF_REG, DPORT_CPUPERIOD_SEL) == DPORT_CPUPERIOD_SEL_240) {
         cpu_freq_mhz = 240;
     }
diff --git a/components/bootloader_support/src/bootloader_common_loader.c b/components/bootloader_support/src/bootloader_common_loader.c
index af11f45fb0b..e958cc462b2 100644
--- a/components/bootloader_support/src/bootloader_common_loader.c
+++ b/components/bootloader_support/src/bootloader_common_loader.c
@@ -22,6 +22,8 @@
 #include "soc/gpio_periph.h"
 #include "soc/rtc.h"
 #include "soc/efuse_reg.h"
+#include "soc/chip_revision.h"
+#include "hal/efuse_ll.h"
 #include "hal/efuse_hal.h"
 #include "soc/soc_memory_types.h"
 #include "hal/gpio_ll.h"
@@ -31,6 +33,7 @@
 #include "bootloader_flash_priv.h"
 
 #define ESP_PARTITION_HASH_LEN 32 /* SHA-256 digest length */
+#define IS_MAX_REV_SET(max_chip_rev_full) (((max_chip_rev_full) != 65535) && ((max_chip_rev_full) != 0))
 
 static const char* TAG = "boot_comm";
 
@@ -60,34 +63,38 @@ int bootloader_common_get_active_otadata(esp_ota_select_entry_t *two_otadata)
     return bootloader_common_select_otadata(two_otadata, valid_two_otadata, true);
 }
 
-esp_err_t bootloader_common_check_chip_validity(const esp_image_header_t* img_hdr, esp_image_type type)
+esp_err_t __attribute__((optimize("-Os"))) bootloader_common_check_chip_validity(const esp_image_header_t* img_hdr, esp_image_type type)
 {
     esp_err_t err = ESP_OK;
     esp_chip_id_t chip_id = CONFIG_IDF_FIRMWARE_CHIP_ID;
     if (chip_id != img_hdr->chip_id) {
         ESP_LOGE(TAG, "mismatch chip ID, expected %d, found %d", chip_id, img_hdr->chip_id);
         err = ESP_FAIL;
-    }
-
+    } else {
 #ifndef CONFIG_IDF_ENV_FPGA
-#if defined(CONFIG_IDF_TARGET_ESP32) || defined(CONFIG_IDF_TARGET_ESP32S2) || defined(CONFIG_IDF_TARGET_ESP32H2)
-    uint8_t revision = efuse_hal_get_major_chip_version();
-    // min_chip_rev keeps the MAJOR wafer version for these chips
-#else
-    uint8_t revision = efuse_hal_get_minor_chip_version();
-    // min_chip_rev keeps the MINOR wafer version for these chips
-#endif
-    if (revision < img_hdr->min_chip_rev) {
-        /* To fix this error, please update mininum supported chip revision from configuration,
-         * located in TARGET (e.g. ESP32) specific options under "Component config" menu */
-        ESP_LOGE(TAG, "This chip is revision %d but the application is configured for minimum revision %d. Can't run.", revision, img_hdr->min_chip_rev);
-        err = ESP_FAIL;
-    } else if (revision != img_hdr->min_chip_rev) {
-#ifdef BOOTLOADER_BUILD
-        ESP_LOGI(TAG, "chip revision: %d, min. %s chip revision: %d", revision, type == ESP_IMAGE_BOOTLOADER ? "bootloader" : "application", img_hdr->min_chip_rev);
-#endif
-    }
+        unsigned revision = efuse_hal_chip_revision();
+        unsigned int major_rev = revision / 100;
+        unsigned int minor_rev = revision % 100;
+        unsigned min_rev = img_hdr->min_chip_rev_full;
+        if (type == ESP_IMAGE_BOOTLOADER || type == ESP_IMAGE_APPLICATION) {
+            if (!ESP_CHIP_REV_ABOVE(revision, min_rev)) {
+                ESP_LOGE(TAG, "Image requires chip rev >= v%d.%d, but chip is v%d.%d",
+                         min_rev / 100, min_rev % 100,
+                         major_rev, minor_rev);
+                err = ESP_FAIL;
+            }
+        }
+        if (type == ESP_IMAGE_APPLICATION) {
+            unsigned max_rev = img_hdr->max_chip_rev_full;
+            if ((IS_MAX_REV_SET(max_rev) && (revision > max_rev) && !efuse_ll_get_disable_wafer_version_major())) {
+                ESP_LOGE(TAG, "Image requires chip rev <= v%d.%d, but chip is v%d.%d",
+                         max_rev / 100, max_rev % 100,
+                         major_rev, minor_rev);
+                err = ESP_FAIL;
+            }
+        }
 #endif // CONFIG_IDF_ENV_FPGA
+    }
 
     return err;
 }
diff --git a/components/bootloader_support/src/bootloader_flash_config_esp32.c b/components/bootloader_support/src/bootloader_flash_config_esp32.c
index cbbc51d4d75..a813b3f99d1 100644
--- a/components/bootloader_support/src/bootloader_flash_config_esp32.c
+++ b/components/bootloader_support/src/bootloader_flash_config_esp32.c
@@ -17,6 +17,7 @@
 #include "soc/spi_reg.h"
 #include "soc/soc_caps.h"
 #include "soc/soc_pins.h"
+#include "soc/chip_revision.h"
 #include "hal/efuse_hal.h"
 #include "hal/gpio_hal.h"
 #include "flash_qio_mode.h"
@@ -169,16 +170,13 @@ int bootloader_flash_get_wp_pin(void)
     return CONFIG_SPIRAM_SPIWP_SD3_PIN; // can be set for app when DIO or DOUT config used for PSRAM only
 #else
     // no custom value, find it based on the package eFuse value
-    uint8_t chip_ver;
-    uint32_t pkg_ver = bootloader_common_get_chip_ver_pkg();
-    switch(pkg_ver) {
+    switch(bootloader_common_get_chip_ver_pkg()) {
     case EFUSE_RD_CHIP_VER_PKG_ESP32U4WDH:
     case EFUSE_RD_CHIP_VER_PKG_ESP32D2WDQ5:
         return ESP32_D2WD_WP_GPIO;
     case EFUSE_RD_CHIP_VER_PKG_ESP32PICOD4:
         /* Same package IDs are used for ESP32-PICO-V3 and ESP32-PICO-D4, silicon version differentiates */
-        chip_ver = efuse_hal_get_major_chip_version();
-        return (chip_ver < 3) ? ESP32_D2WD_WP_GPIO : ESP32_PICO_V3_GPIO;
+        return !ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 300) ? ESP32_D2WD_WP_GPIO : ESP32_PICO_V3_GPIO;
     case EFUSE_RD_CHIP_VER_PKG_ESP32PICOV302:
         return ESP32_PICO_V3_GPIO;
     default:
diff --git a/components/bootloader_support/src/esp32c3/bootloader_esp32c3.c b/components/bootloader_support/src/esp32c3/bootloader_esp32c3.c
index 2eedfe81ef4..fe9d94cfca2 100644
--- a/components/bootloader_support/src/esp32c3/bootloader_esp32c3.c
+++ b/components/bootloader_support/src/esp32c3/bootloader_esp32c3.c
@@ -23,6 +23,7 @@
 #include "soc/extmem_reg.h"
 #include "soc/io_mux_reg.h"
 #include "soc/system_reg.h"
+#include "soc/chip_revision.h"
 #include "esp32c3/rom/efuse.h"
 #include "esp32c3/rom/spi_flash.h"
 #include "esp32c3/rom/cache.h"
@@ -259,7 +260,7 @@ static inline void bootloader_hardware_init(void)
 {
     // This check is always included in the bootloader so it can
     // print the minimum revision error message later in the boot
-    if (efuse_hal_get_minor_chip_version() < 3) {
+    if (!ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 3)) {
         REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_FORCE_XPD_IPH, 1);
         REGI2C_WRITE_MASK(I2C_BIAS, I2C_BIAS_DREG_1P1_PVT, 12);
     }
@@ -272,8 +273,7 @@ static inline void bootloader_ana_reset_config(void)
       For ECO2: fix brownout reset bug, support swt & brownout reset;
       For ECO3: fix clock glitch reset bug, support all reset, include: swt & brownout & clock glitch reset.
     */
-    uint8_t chip_version = efuse_hal_get_minor_chip_version();
-    switch (chip_version) {
+    switch (efuse_hal_chip_revision()) {
         case 0:
         case 1:
             //Enable WDT reset. Disable BOR and GLITCH reset
diff --git a/components/efuse/esp32/esp_efuse_fields.c b/components/efuse/esp32/esp_efuse_fields.c
index 0cab6087eae..657cbdf2fef 100644
--- a/components/efuse/esp32/esp_efuse_fields.c
+++ b/components/efuse/esp32/esp_efuse_fields.c
@@ -13,6 +13,7 @@
 #include "esp_err.h"
 #include "esp_log.h"
 #include "soc/efuse_periph.h"
+#include "soc/chip_revision.h"
 #include "hal/efuse_hal.h"
 #include "bootloader_random.h"
 #include "sys/param.h"
@@ -41,9 +42,9 @@ void esp_efuse_disable_basic_rom_console(void)
 
 esp_err_t esp_efuse_disable_rom_download_mode(void)
 {
-#ifndef CONFIG_ESP32_REV_MIN_3
+#if CONFIG_ESP32_REV_MIN_FULL < 300
     /* Check if we support this revision at all */
-    if (efuse_hal_get_major_chip_version() < 3) {
+    if (!ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 300)) {
         return ESP_ERR_NOT_SUPPORTED;
     }
 #endif
diff --git a/components/efuse/include/esp_efuse.h b/components/efuse/include/esp_efuse.h
index f2c08bad30e..d869a2e84b0 100644
--- a/components/efuse/include/esp_efuse.h
+++ b/components/efuse/include/esp_efuse.h
@@ -741,7 +741,7 @@ esp_err_t esp_efuse_write_key(esp_efuse_block_t block, esp_efuse_purpose_t purpo
 esp_err_t esp_efuse_write_keys(const esp_efuse_purpose_t purposes[], uint8_t keys[][32], unsigned number_of_keys);
 
 
-#if CONFIG_ESP32_REV_MIN_3 || !CONFIG_IDF_TARGET_ESP32
+#if CONFIG_ESP32_REV_MIN_FULL >= 300 || !CONFIG_IDF_TARGET_ESP32
 /**
  * @brief Read key digests from efuse. Any revoked/missing digests will be marked as NULL
  *
diff --git a/components/efuse/src/esp_efuse_api_key_esp32.c b/components/efuse/src/esp_efuse_api_key_esp32.c
index 59ec9eb30e2..52ae4b20902 100644
--- a/components/efuse/src/esp_efuse_api_key_esp32.c
+++ b/components/efuse/src/esp_efuse_api_key_esp32.c
@@ -233,7 +233,7 @@ esp_err_t esp_efuse_write_keys(const esp_efuse_purpose_t purposes[], uint8_t key
     return err;
 }
 
-#if CONFIG_ESP32_REV_MIN_3
+#if CONFIG_ESP32_REV_MIN_FULL >= 300
 esp_err_t esp_secure_boot_read_key_digests(ets_secure_boot_key_digests_t *trusted_keys)
 {
     if (trusted_keys == NULL) {
@@ -242,4 +242,4 @@ esp_err_t esp_secure_boot_read_key_digests(ets_secure_boot_key_digests_t *truste
     trusted_keys->key_digests[0] = (const void *)esp_efuse_utility_get_read_register_address(EFUSE_BLK_SECURE_BOOT);
     return ESP_OK;
 }
-#endif // CONFIG_ESP32_REV_MIN_3
+#endif // CONFIG_ESP32_REV_MIN_FULL >= 300
diff --git a/components/esp32/Kconfig b/components/esp32/Kconfig
index 3b65e05d6e8..754ca607b8b 100644
--- a/components/esp32/Kconfig
+++ b/components/esp32/Kconfig
@@ -13,30 +13,77 @@ menu "ESP32-specific"
         prompt "Minimum Supported ESP32 Revision"
         default ESP32_REV_MIN_0
         help
-            Minimum revision that ESP-IDF would support.
-            ESP-IDF performs different strategy on different esp32 revision.
+            Required minimum chip revision. ESP-IDF will check for it and
+            reject to boot if the chip revision fails the check.
+            This ensures the chip used will have some modifications (features, or bugfixes).
+
+            The complied binary will only support chips above this revision,
+            this will also help to reduce binary size.
 
         config ESP32_REV_MIN_0
-            bool "Rev 0"
+            bool "Rev v0.0 (ECO0)"
         config ESP32_REV_MIN_1
-            bool "Rev 1"
+            bool "Rev v1.0 (ECO1)"
+        config ESP32_REV_MIN_1_1
+            bool "Rev v1.1 (ECO1.1)"
         config ESP32_REV_MIN_2
-            bool "Rev 2"
+            bool "Rev v2.0 (ECO2)"
         config ESP32_REV_MIN_3
-            bool "Rev 3"
+            bool "Rev v3.0 (ECO3)"
+            select ESP_INT_WDT if ESP32_ECO3_CACHE_LOCK_FIX
+        config ESP32_REV_MIN_3_1
+            bool "Rev v3.1 (ECO4)"
             select ESP_INT_WDT if ESP32_ECO3_CACHE_LOCK_FIX
     endchoice
 
     config ESP32_REV_MIN
+        # we keep it for compatibility. Use ESP32_REV_MIN_FULL instead.
         int
         default 0 if ESP32_REV_MIN_0
-        default 1 if ESP32_REV_MIN_1
+        default 1 if ESP32_REV_MIN_1 || ESP32_REV_MIN_1_1
         default 2 if ESP32_REV_MIN_2
-        default 3 if ESP32_REV_MIN_3
+        default 3 if ESP32_REV_MIN_3 || ESP32_REV_MIN_3_1
+
+    config ESP32_REV_MIN_FULL
+        int
+        default 0 if ESP32_REV_MIN_0
+        default 100 if ESP32_REV_MIN_1
+        default 101 if ESP32_REV_MIN_1_1
+        default 200 if ESP32_REV_MIN_2
+        default 300 if ESP32_REV_MIN_3
+        default 301 if ESP32_REV_MIN_3_1
+
+    config ESP_REV_MIN_FULL
+        int
+        default ESP32_REV_MIN_FULL
+
+        #
+        # MAX Revision
+        #
+
+    choice ESP32_REV_MAX_FULL_STR
+        prompt "Maximum Supported ESP32 Revision"
+        config ESP32_REV_MAX_FULL_STR_OPT
+            bool "Rev v3.99"
+    endchoice
+
+    # Maximum revision that IDF supports.
+    # It can not be changed by user.
+    # Only Espressif can change it when a new version will be supported in IDF.
+    # Supports all chips starting from ESP32_REV_MIN_FULL to ESP32_REV_MAX_FULL
+
+    config ESP32_REV_MAX_FULL
+        int
+        default 399
+        # keep in sync the "Maximum Supported Revision" description with this value
+
+    config ESP_REV_MAX_FULL
+        int
+        default ESP32_REV_MAX_FULL
 
     config ESP32_DPORT_WORKAROUND
         bool
-        default "y" if !FREERTOS_UNICORE  && ESP32_REV_MIN < 2
+        default "y" if !FREERTOS_UNICORE  && ESP32_REV_MIN_FULL < 200
 
     choice ESP32_DEFAULT_CPU_FREQ_MHZ
         prompt "CPU frequency"
@@ -131,7 +178,7 @@ menu "ESP32-specific"
 
         config SPIRAM_CACHE_WORKAROUND
             bool "Enable workaround for bug in SPI RAM cache for Rev1 ESP32s"
-            depends on (SPIRAM_USE_MEMMAP || SPIRAM_USE_CAPS_ALLOC || SPIRAM_USE_MALLOC) && (ESP32_REV_MIN < 3)
+            depends on (SPIRAM_USE_MEMMAP || SPIRAM_USE_CAPS_ALLOC || SPIRAM_USE_MALLOC) && (ESP32_REV_MIN_FULL < 300)
             default "y"
             help
                 Revision 1 of the ESP32 has a bug that can cause a write to PSRAM not to take place in some situations
@@ -654,7 +701,7 @@ menu "ESP32-specific"
     choice ESP32_RTC_EXT_CRYST_ADDIT_CURRENT_METHOD
         prompt "Additional current for external 32kHz crystal"
         depends on ESP32_RTC_CLK_SRC_EXT_CRYS
-        depends on ESP32_REV_MIN <= 1
+        depends on ESP32_REV_MIN_FULL < 200
         default ESP32_RTC_EXT_CRYST_ADDIT_CURRENT_NONE
         help
             With some 32kHz crystal configurations, the X32N and X32P pins may not have enough
diff --git a/components/esp32c3/Kconfig b/components/esp32c3/Kconfig
index 5c7c072c46b..a25bb5f415d 100644
--- a/components/esp32c3/Kconfig
+++ b/components/esp32c3/Kconfig
@@ -27,23 +27,27 @@ menu "ESP32C3-Specific"
         prompt "Minimum Supported ESP32-C3 Revision"
         default ESP32C3_REV_MIN_3
         help
-            Minimum revision that ESP-IDF would support.
+            Required minimum chip revision. ESP-IDF will check for it and
+            reject to boot if the chip revision fails the check.
+            This ensures the chip used will have some modifications (features, or bugfixes).
 
-            Only supporting higher chip revisions can reduce binary size.
+            The complied binary will only support chips above this revision,
+            this will also help to reduce binary size.
 
         config ESP32C3_REV_MIN_0
-            bool "Rev 0"
+            bool "Rev v0.0 (ECO0)"
         config ESP32C3_REV_MIN_1
-            bool "Rev 1"
+            bool "Rev v0.1 (ECO1)"
         config ESP32C3_REV_MIN_2
-            bool "Rev 2"
+            bool "Rev v0.2 (ECO2)"
         config ESP32C3_REV_MIN_3
-            bool "Rev 3"
+            bool "Rev v0.3 (ECO3)"
         config ESP32C3_REV_MIN_4
-            bool "Rev 4"
+            bool "Rev v0.4 (ECO4)"
     endchoice
 
     config ESP32C3_REV_MIN
+        # we keep it for compatibility. Use ESP32C3_REV_MIN_FULL instead.
         int
         default 0 if ESP32C3_REV_MIN_0
         default 1 if ESP32C3_REV_MIN_1
@@ -51,6 +55,43 @@ menu "ESP32C3-Specific"
         default 3 if ESP32C3_REV_MIN_3
         default 4 if ESP32C3_REV_MIN_4
 
+    config ESP32C3_REV_MIN_FULL
+        int
+        default 0 if ESP32C3_REV_MIN_0
+        default 1 if ESP32C3_REV_MIN_1
+        default 2 if ESP32C3_REV_MIN_2
+        default 3 if ESP32C3_REV_MIN_3
+        default 4 if ESP32C3_REV_MIN_4
+
+    config ESP_REV_MIN_FULL
+        int
+        default ESP32C3_REV_MIN_FULL
+
+        #
+        # MAX Revision
+        #
+
+    choice ESP32C3_REV_MAX_FULL_STR
+        prompt "Maximum Supported ESP32-C3 Revision"
+        config ESP32C3_REV_MAX_FULL_STR_OPT
+            bool "Rev v0.99"
+    endchoice
+
+    # Maximum revision that IDF supports.
+    # It can not be changed by user.
+    # Only Espressif can change it when a new version will be supported in IDF.
+    # Supports all chips starting from ESP32C3_REV_MIN_FULL to ESP32C3_REV_MAX_FULL
+
+    config ESP32C3_REV_MAX_FULL
+        int
+        default 99
+        # keep in sync the "Maximum Supported Revision" description with this value
+
+    config ESP_REV_MAX_FULL
+        int
+        default ESP32C3_REV_MAX_FULL
+
+
     config ESP32C3_DEBUG_OCDAWARE
         bool "Make exception and panic handlers JTAG/OCD aware"
         default y
diff --git a/components/esp32h2/Kconfig b/components/esp32h2/Kconfig
index a172bd0023c..4aa50941fed 100644
--- a/components/esp32h2/Kconfig
+++ b/components/esp32h2/Kconfig
@@ -1,6 +1,53 @@
 menu "ESP32H2-Specific"
     visible if IDF_TARGET_ESP32H2
 
+    choice ESP32H2_REV_MIN
+        prompt "Minimum Supported ESP32-H2 Revision"
+        default ESP32H2_REV_MIN_0
+        help
+            Required minimum chip revision. ESP-IDF will check for it and
+            reject to boot if the chip revision fails the check.
+            This ensures the chip used will have some modifications (features, or bugfixes).
+
+            The complied binary will only support chips above this revision,
+            this will also help to reduce binary size.
+
+        config ESP32H2_REV_MIN_0
+            bool "Rev v0.0 (ECO0)"
+    endchoice
+
+    config ESP32H2_REV_MIN_FULL
+        int
+        default 0 if ESP32H2_REV_MIN_0
+
+    config ESP_REV_MIN_FULL
+        int
+        default ESP32H2_REV_MIN_FULL
+
+        #
+        # MAX Revision
+        #
+
+    choice ESP32H2_REV_MAX_FULL_STR
+        prompt "Maximum Supported ESP32-H2 Revision"
+        config ESP32H2_REV_MAX_FULL_STR_OPT
+            bool "Rev v0.99"
+    endchoice
+
+    # Maximum revision that IDF supports.
+    # It can not be changed by user.
+    # Only Espressif can change it when a new version will be supported in IDF.
+    # Supports all chips starting from ESP32H2_REV_MIN_FULL to ESP32H2_REV_MAX_FULL
+
+    config ESP32H2_REV_MAX_FULL
+        int
+        default 99
+        # keep in sync the "Maximum Supported Revision" description with this value
+
+    config ESP_REV_MAX_FULL
+        int
+        default ESP32H2_REV_MAX_FULL
+
     choice ESP32H2_DEFAULT_CPU_FREQ_MHZ
         prompt "CPU frequency"
         default ESP32H2_DEFAULT_CPU_FREQ_64 if IDF_ENV_FPGA
diff --git a/components/esp32s2/Kconfig b/components/esp32s2/Kconfig
index 0e0a092ca94..6733568c647 100644
--- a/components/esp32s2/Kconfig
+++ b/components/esp32s2/Kconfig
@@ -4,6 +4,56 @@ menu "ESP32S2-specific"
     # not working so we just hide all items here
     visible if IDF_TARGET_ESP32S2
 
+    choice ESP32S2_REV_MIN
+        prompt "Minimum Supported ESP32-S2 Revision"
+        default ESP32S2_REV_MIN_0
+        help
+            Required minimum chip revision. ESP-IDF will check for it and
+            reject to boot if the chip revision fails the check.
+            This ensures the chip used will have some modifications (features, or bugfixes).
+
+            The complied binary will only support chips above this revision,
+            this will also help to reduce binary size.
+
+        config ESP32S2_REV_MIN_0
+            bool "Rev v0.0 (ECO0)"
+        config ESP32S2_REV_MIN_1
+            bool "Rev v1.0 (ECO1)"
+    endchoice
+
+    config ESP32S2_REV_MIN_FULL
+        int
+        default 0   if ESP32S2_REV_MIN_0
+        default 100 if ESP32S2_REV_MIN_1
+
+    config ESP_REV_MIN_FULL
+        int
+        default ESP32S2_REV_MIN_FULL
+
+        #
+        # MAX Revision
+        #
+
+    choice ESP32S2_REV_MAX_FULL_STR
+        prompt "Maximum Supported ESP32-S2 Revision"
+        config ESP32S2_REV_MAX_FULL_STR_OPT
+            bool "Rev v1.99"
+    endchoice
+
+    # Maximum revision that IDF supports.
+    # It can not be changed by user.
+    # Only Espressif can change it when a new version will be supported in IDF.
+    # Supports all chips starting from ESP32S2_REV_MIN_FULL to ESP32S2_REV_MAX_FULL
+
+    config ESP32S2_REV_MAX_FULL
+        int
+        default 199
+        # keep in sync the "Maximum Supported Revision" description with this value
+
+    config ESP_REV_MAX_FULL
+        int
+        default ESP32S2_REV_MAX_FULL
+
     choice ESP32S2_DEFAULT_CPU_FREQ_MHZ
         prompt "CPU frequency"
         default ESP32S2_DEFAULT_CPU_FREQ_160 if !IDF_ENV_FPGA
diff --git a/components/esp32s3/Kconfig b/components/esp32s3/Kconfig
index c9b72371807..53f2e498c95 100644
--- a/components/esp32s3/Kconfig
+++ b/components/esp32s3/Kconfig
@@ -1,6 +1,59 @@
 menu "ESP32S3-Specific"
     visible if IDF_TARGET_ESP32S3
 
+    choice ESP32S3_REV_MIN
+        prompt "Minimum Supported ESP32-S3 Revision"
+        default ESP32S3_REV_MIN_0
+        help
+            Required minimum chip revision. ESP-IDF will check for it and
+            reject to boot if the chip revision fails the check.
+            This ensures the chip used will have some modifications (features, or bugfixes).
+
+            The complied binary will only support chips above this revision,
+            this will also help to reduce binary size.
+
+        config ESP32S3_REV_MIN_0
+            bool "Rev v0.0 (ECO0)"
+        config ESP32S3_REV_MIN_1
+            bool "Rev v0.1 (ECO1)"
+        config ESP32S3_REV_MIN_2
+            bool "Rev v0.2 (ECO2)"
+    endchoice
+
+    config ESP32S3_REV_MIN_FULL
+        int
+        default 0 if ESP32S3_REV_MIN_0
+        default 1 if ESP32S3_REV_MIN_1
+        default 2 if ESP32S3_REV_MIN_2
+
+    config ESP_REV_MIN_FULL
+        int
+        default ESP32S3_REV_MIN_FULL
+
+        #
+        # MAX Revision
+        #
+
+    choice ESP32S3_REV_MAX_FULL_STR
+        prompt "Maximum Supported ESP32-S3 Revision"
+        config ESP32S3_REV_MAX_FULL_STR_OPT
+            bool "Rev v0.99"
+    endchoice
+
+    # Maximum revision that IDF supports.
+    # It can not be changed by user.
+    # Only Espressif can change it when a new version will be supported in IDF.
+    # Supports all chips starting from ESP32S3_REV_MIN_FULL to ESP32S3_REV_MAX_FULL
+
+    config ESP32S3_REV_MAX_FULL
+        int
+        default 99
+        # keep in sync the "Maximum Supported Revision" description with this value
+
+    config ESP_REV_MAX_FULL
+        int
+        default ESP32S3_REV_MAX_FULL
+
     choice ESP32S3_DEFAULT_CPU_FREQ_MHZ
         prompt "CPU frequency"
         default ESP32S3_DEFAULT_CPU_FREQ_40 if IDF_ENV_FPGA
diff --git a/components/esp_hw_support/port/esp32/chip_info.c b/components/esp_hw_support/port/esp32/chip_info.c
index 5ad5f339237..16ca063d1b0 100644
--- a/components/esp_hw_support/port/esp32/chip_info.c
+++ b/components/esp_hw_support/port/esp32/chip_info.c
@@ -7,6 +7,7 @@
 #include <string.h>
 #include "esp_chip_info.h"
 #include "soc/soc.h"
+#include "soc/chip_revision.h"
 #include "soc/efuse_reg.h"
 #include "esp_efuse.h"
 #include "hal/efuse_hal.h"
@@ -44,6 +45,7 @@ void esp_chip_info(esp_chip_info_t* out_info)
 #if CONFIG_ESP32_ECO3_CACHE_LOCK_FIX
 inline bool soc_has_cache_lock_bug(void)
 {
-    return (efuse_hal_get_major_chip_version() == 3);
+    unsigned rev = efuse_hal_chip_revision();
+    return ESP_CHIP_REV_ABOVE(rev, 300);
 }
 #endif
diff --git a/components/esp_hw_support/port/esp32/rtc_clk.c b/components/esp_hw_support/port/esp32/rtc_clk.c
index 0124564a29d..9f0a70b6617 100644
--- a/components/esp_hw_support/port/esp32/rtc_clk.c
+++ b/components/esp_hw_support/port/esp32/rtc_clk.c
@@ -16,6 +16,8 @@
 #include "soc/rtc_periph.h"
 #include "soc/sens_periph.h"
 #include "soc/dport_reg.h"
+#include "soc/soc_caps.h"
+#include "soc/chip_revision.h"
 #include "hal/efuse_ll.h"
 #include "hal/efuse_hal.h"
 #include "soc/efuse_periph.h"
@@ -124,9 +126,8 @@ static void rtc_clk_32k_enable_common(int dac, int dres, int dbias)
     REG_SET_FIELD(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_DBIAS_XTAL_32K, dbias);
 
 #ifdef CONFIG_ESP32_RTC_EXT_CRYST_ADDIT_CURRENT
-    uint8_t chip_ver = efuse_hal_get_major_chip_version();
     // version0 and version1 need provide additional current to external XTAL.
-    if(chip_ver == 0 || chip_ver == 1) {
+    if (!ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 200)) {
         /* TOUCH sensor can provide additional current to external XTAL.
         In some case, X32N and X32P PAD don't have enough drive capability to start XTAL */
         SET_PERI_REG_MASK(RTC_IO_TOUCH_CFG_REG, RTC_IO_TOUCH_XPD_BIAS_M);
@@ -140,8 +141,7 @@ static void rtc_clk_32k_enable_common(int dac, int dres, int dbias)
         SET_PERI_REG_MASK(RTC_IO_TOUCH_PAD9_REG, RTC_IO_TOUCH_PAD9_XPD_M);
     }
 #elif defined CONFIG_ESP32_RTC_EXT_CRYST_ADDIT_CURRENT_V2
-    uint8_t chip_ver = efuse_hal_get_major_chip_version();
-    if(chip_ver == 0 || chip_ver == 1) {
+    if (!ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 200)) {
         /* TOUCH sensor can provide additional current to external XTAL.
         In some case, X32N and X32P PAD don't have enough drive capability to start XTAL */
         SET_PERI_REG_MASK(RTC_IO_TOUCH_CFG_REG, RTC_IO_TOUCH_XPD_BIAS_M);
@@ -174,14 +174,12 @@ void rtc_clk_32k_enable(bool enable)
         CLEAR_PERI_REG_MASK(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_X32N_MUX_SEL | RTC_IO_X32P_MUX_SEL);
 
 #ifdef CONFIG_ESP32_RTC_EXT_CRYST_ADDIT_CURRENT
-        uint8_t chip_ver = efuse_hal_get_major_chip_version();
-        if(chip_ver == 0 || chip_ver == 1) {
+        if (!ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 200)) {
             /* Power down TOUCH */
             CLEAR_PERI_REG_MASK(RTC_IO_TOUCH_PAD9_REG, RTC_IO_TOUCH_PAD9_XPD_M);
         }
 #elif defined CONFIG_ESP32_RTC_EXT_CRYST_ADDIT_CURRENT_V2
-        uint8_t chip_ver = efuse_hal_get_major_chip_version();
-        if(chip_ver == 0 || chip_ver == 1) {
+        if (!ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 200)) {
             /* Power down TOUCH */
             CLEAR_PERI_REG_MASK(RTC_IO_TOUCH_CFG_REG, RTC_IO_TOUCH_XPD_BIAS_M);
             SET_PERI_REG_BITS(RTC_IO_TOUCH_CFG_REG, RTC_IO_TOUCH_DCUR, 0, RTC_IO_TOUCH_DCUR_S);
@@ -283,7 +281,7 @@ void rtc_clk_apll_enable(bool enable, uint32_t sdm0, uint32_t sdm1, uint32_t sdm
 
     if (enable) {
         uint8_t sdm_stop_val_2 = APLL_SDM_STOP_VAL_2_REV1;
-        if (efuse_hal_get_major_chip_version() == 0) {
+        if (!ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 100)) {
             sdm0 = 0;
             sdm1 = 0;
             sdm_stop_val_2 = APLL_SDM_STOP_VAL_2_REV0;
diff --git a/components/esp_hw_support/port/esp32/spiram_psram.c b/components/esp_hw_support/port/esp32/spiram_psram.c
index a4f36cd6dc7..620a00e95ea 100644
--- a/components/esp_hw_support/port/esp32/spiram_psram.c
+++ b/components/esp_hw_support/port/esp32/spiram_psram.c
@@ -24,6 +24,7 @@
 #include "soc/dport_reg.h"
 #include "soc/efuse_periph.h"
 #include "soc/soc_caps.h"
+#include "soc/chip_revision.h"
 #include "driver/gpio.h"
 #include "hal/efuse_hal.h"
 #include "hal/efuse_ll.h"
@@ -833,7 +834,7 @@ esp_err_t IRAM_ATTR psram_enable(psram_cache_mode_t mode, psram_vaddr_mode_t vad
         }
         psram_io.psram_clk_io = D2WD_PSRAM_CLK_IO;
         psram_io.psram_cs_io  = D2WD_PSRAM_CS_IO;
-    } else if (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD4 && efuse_hal_get_major_chip_version() >= 3) {
+    } else if (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD4 && ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 300)) {
         ESP_EARLY_LOGE(TAG, "This chip is ESP32-PICO-V3. It does not support PSRAM (disable it in Kconfig)");
         abort();
     } else if ((pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD2) || (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD4)) {
diff --git a/components/esp_hw_support/port/esp32c3/rtc_init.c b/components/esp_hw_support/port/esp32c3/rtc_init.c
index bb1966e6fa3..3511bda87ca 100644
--- a/components/esp_hw_support/port/esp32c3/rtc_init.c
+++ b/components/esp_hw_support/port/esp32c3/rtc_init.c
@@ -317,7 +317,7 @@ static void set_rtc_dig_dbias()
     3. a reasonable rtc_dbias can be calculated by a certion formula.
     */
     uint32_t rtc_dbias = 28, dig_dbias = 28;
-    uint8_t chip_version = efuse_hal_get_minor_chip_version();
+    unsigned chip_version = efuse_hal_chip_revision();
     if (chip_version >= 3) {
         dig_dbias = get_dig_dbias_by_efuse(chip_version);
         if (dig_dbias != 0) {
diff --git a/components/esp_hw_support/port/esp32c3/rtc_sleep.c b/components/esp_hw_support/port/esp32c3/rtc_sleep.c
index 4a7f4e61674..3fc6c61c3d5 100644
--- a/components/esp_hw_support/port/esp32c3/rtc_sleep.c
+++ b/components/esp_hw_support/port/esp32c3/rtc_sleep.c
@@ -18,6 +18,7 @@
 #include "soc/timer_group_reg.h"
 #include "soc/system_reg.h"
 #include "soc/rtc.h"
+#include "soc/chip_revision.h"
 #include "esp32c3/rom/ets_sys.h"
 #include "esp32c3/rom/rtc.h"
 #include "regi2c_ctrl.h"
@@ -77,8 +78,8 @@ void rtc_sleep_get_default_config(uint32_t sleep_flags, rtc_sleep_config_t *out_
 
     if (sleep_flags & RTC_SLEEP_PD_DIG) {
         unsigned atten_deep_sleep = RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT;
-#if CONFIG_ESP32C3_REV_MIN < 3
-        if (efuse_hal_get_minor_chip_version() < 3) {
+#if CONFIG_ESP32C3_REV_MIN_FULL < 3
+        if (!ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 3)) {
             atten_deep_sleep = 0; /* workaround for deep sleep issue in high temp on ECO2 and below */
         }
 #endif
diff --git a/components/esp_phy/src/phy_init.c b/components/esp_phy/src/phy_init.c
index 36110cde57b..da7d11bdf39 100644
--- a/components/esp_phy/src/phy_init.c
+++ b/components/esp_phy/src/phy_init.c
@@ -667,7 +667,7 @@ void esp_phy_load_cal_and_init(void)
     ESP_LOGI(TAG, "phy_version %s", phy_version);
 
 #if CONFIG_IDF_TARGET_ESP32S2
-    phy_eco_version_sel(efuse_hal_get_major_chip_version());
+    phy_eco_version_sel(efuse_hal_chip_revision() / 100);
 #endif
     esp_phy_calibration_data_t* cal_data =
             (esp_phy_calibration_data_t*) calloc(sizeof(esp_phy_calibration_data_t), 1);
diff --git a/components/esp_rom/CMakeLists.txt b/components/esp_rom/CMakeLists.txt
index 19388d9f0fa..290dce049f8 100644
--- a/components/esp_rom/CMakeLists.txt
+++ b/components/esp_rom/CMakeLists.txt
@@ -53,7 +53,7 @@ if(BOOTLOADER_BUILD)
         if(NOT CONFIG_SPI_FLASH_ROM_DRIVER_PATCH)
             rom_linker_script("spiflash")
         endif()
-        if(CONFIG_ESP32_REV_MIN_3)
+        if(CONFIG_ESP32_REV_MIN_FULL EQUAL 300 OR CONFIG_ESP32_REV_MIN_FULL GREATER 300)
             rom_linker_script("eco3")
         endif()
 
@@ -97,7 +97,7 @@ else() # Regular app build
             rom_linker_script("spiflash")
         endif()
 
-        if(CONFIG_ESP32_REV_MIN_3)
+        if(CONFIG_ESP32_REV_MIN_FULL EQUAL 300 OR CONFIG_ESP32_REV_MIN_FULL GREATER 300)
             rom_linker_script("eco3")
         endif()
 
@@ -154,7 +154,7 @@ else() # Regular app build
             rom_linker_script("newlib-time")
         endif()
 
-        if(CONFIG_ESP32C3_REV_MIN_3 OR CONFIG_ESP32C3_REV_MIN_4)
+        if(CONFIG_ESP32C3_REV_MIN_FULL EQUAL 3 OR CONFIG_ESP32C3_REV_MIN_FULL GREATER 3)
             rom_linker_script("eco3")
         endif()
 
diff --git a/components/esp_rom/component.mk b/components/esp_rom/component.mk
index c68101573e4..f6bcd22b7f5 100644
--- a/components/esp_rom/component.mk
+++ b/components/esp_rom/component.mk
@@ -19,7 +19,7 @@ LINKER_SCRIPTS += esp32.rom.ld \
 ifndef CONFIG_SPIRAM_CACHE_WORKAROUND
 LINKER_SCRIPTS += esp32.rom.newlib-funcs.ld
 
-ifdef CONFIG_ESP32_REV_MIN_3
+ifeq ($(shell expr $(CONFIG_ESP32_REV_MIN_FULL) \>= 300), 1)
 LINKER_SCRIPTS += esp32.rom.eco3.ld
 endif
 
diff --git a/components/esp_rom/include/esp32/rom/rsa_pss.h b/components/esp_rom/include/esp32/rom/rsa_pss.h
index bfc1e68cdab..9c6979484dc 100644
--- a/components/esp_rom/include/esp32/rom/rsa_pss.h
+++ b/components/esp_rom/include/esp32/rom/rsa_pss.h
@@ -1,21 +1,13 @@
-// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 
 #pragma once
 
 #include "sdkconfig.h"
-#ifdef CONFIG_ESP32_REV_MIN_3
+#if CONFIG_ESP32_REV_MIN_FULL >= 300
 
 #include <stdint.h>
 #include <stdbool.h>
@@ -47,4 +39,4 @@ bool ets_emsa_pss_verify(const uint8_t *encoded_message, const uint8_t *mhash, u
 }
 #endif
 
-#endif // CONFIG_ESP32_REV_MIN_3
+#endif // CONFIG_ESP32_REV_MIN_FULL >= 300
diff --git a/components/esp_rom/include/esp32/rom/secure_boot.h b/components/esp_rom/include/esp32/rom/secure_boot.h
index 04c3c509f78..166e2e34c46 100644
--- a/components/esp_rom/include/esp32/rom/secure_boot.h
+++ b/components/esp_rom/include/esp32/rom/secure_boot.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -34,7 +34,7 @@ bool ets_secure_boot_check_start(uint8_t abs_index, uint32_t iv_addr);
 
 int ets_secure_boot_check_finish(uint32_t *abstract);
 
-#ifdef CONFIG_ESP32_REV_MIN_3
+#if CONFIG_ESP32_REV_MIN_FULL >= 300
 #include "rsa_pss.h"
 
 #define SECURE_BOOT_NUM_BLOCKS 1
@@ -115,7 +115,7 @@ bool ets_use_secure_boot_v2(void);
 #else
 #define SECURE_BOOT_NUM_BLOCKS 0
 
-#endif /* CONFIG_ESP32_REV_MIN_3 */
+#endif /* CONFIG_ESP32_REV_MIN_FULL >= 300 */
 
 #ifdef __cplusplus
 }
diff --git a/components/esp_system/startup.c b/components/esp_system/startup.c
index 2bf5a8fbd92..e3ad0345f28 100644
--- a/components/esp_system/startup.c
+++ b/components/esp_system/startup.c
@@ -20,6 +20,8 @@
 #include "hal/wdt_hal.h"
 #include "hal/uart_types.h"
 #include "hal/uart_ll.h"
+#include "hal/efuse_ll.h"
+#include "hal/efuse_hal.h"
 
 #include "esp_system.h"
 #include "esp_log.h"
@@ -427,6 +429,12 @@ static void start_cpu0_default(void)
         esp_ota_get_app_elf_sha256(buf, sizeof(buf));
         ESP_EARLY_LOGI(TAG, "ELF file SHA256:  %s...", buf);
         ESP_EARLY_LOGI(TAG, "ESP-IDF:          %s", app_desc->idf_ver);
+
+        ESP_EARLY_LOGI(TAG, "Min chip rev:     v%d.%d", CONFIG_ESP_REV_MIN_FULL / 100, CONFIG_ESP_REV_MIN_FULL % 100);
+        ESP_EARLY_LOGI(TAG, "Max chip rev:     v%d.%d %s",CONFIG_ESP_REV_MAX_FULL / 100, CONFIG_ESP_REV_MAX_FULL % 100,
+                       efuse_ll_get_disable_wafer_version_major() ? "(constraint ignored)" : "");
+        unsigned revision = efuse_hal_chip_revision();
+        ESP_EARLY_LOGI(TAG, "Chip rev:         v%d.%d", revision / 100, revision % 100);
     }
 
     // Initialize core components and services.
diff --git a/components/esp_system/test/test_reset_reason.c b/components/esp_system/test/test_reset_reason.c
index 7273656fa15..5ce8a5e4045 100644
--- a/components/esp_system/test/test_reset_reason.c
+++ b/components/esp_system/test/test_reset_reason.c
@@ -32,11 +32,11 @@ static RTC_SLOW_ATTR uint32_t s_rtc_force_slow_val;
 #define INT_WDT_PANIC       "Interrupt wdt timeout on CPU0"
 #define INT_WDT             "TG1WDT_SYS_RESET"
 #define RTC_WDT             "RTCWDT_RTC_RESET"
-#ifdef CONFIG_ESP32_REV_MIN_3
+#if CONFIG_ESP32_REV_MIN_FULL >= 300
 #define BROWNOUT            "RTCWDT_BROWN_OUT_RESET"
 #else
 #define BROWNOUT            "SW_CPU_RESET"
-#endif // CONFIG_ESP32_REV_MIN_3
+#endif // CONFIG_ESP32_REV_MIN_FULL >= 300
 #define STORE_ERROR         "StoreProhibited"
 
 #elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
diff --git a/components/esptool_py/Makefile.projbuild b/components/esptool_py/Makefile.projbuild
index 2311d7497d4..6253414957d 100644
--- a/components/esptool_py/Makefile.projbuild
+++ b/components/esptool_py/Makefile.projbuild
@@ -39,6 +39,9 @@ ifdef CONFIG_ESP32_REV_MIN
 ESPTOOL_ELF2IMAGE_OPTIONS += --min-rev $(CONFIG_ESP32_REV_MIN)
 endif
 
+ESPTOOL_ELF2IMAGE_OPTIONS += --min-rev-full $(CONFIG_ESP_REV_MIN_FULL)
+ESPTOOL_ELF2IMAGE_OPTIONS += --max-rev-full $(CONFIG_ESP_REV_MAX_FULL)
+
 ifndef CONFIG_SECURE_BOOT_ALLOW_SHORT_APP_PARTITION
 ifndef IS_BOOTLOADER_BUILD
 ifdef CONFIG_SECURE_SIGNED_APPS_ECDSA_SCHEME
diff --git a/components/esptool_py/esptool b/components/esptool_py/esptool
index 4bc311767b7..0299c38f103 160000
--- a/components/esptool_py/esptool
+++ b/components/esptool_py/esptool
@@ -1 +1 @@
-Subproject commit 4bc311767b7c6df41def6f95a50f87b1c9406cbd
+Subproject commit 0299c38f103d38a61bc1715abe8965cf88fab4b7
diff --git a/components/esptool_py/project_include.cmake b/components/esptool_py/project_include.cmake
index 0d666a22baf..c9a7fd27d8e 100644
--- a/components/esptool_py/project_include.cmake
+++ b/components/esptool_py/project_include.cmake
@@ -61,19 +61,25 @@ if(NOT CONFIG_SECURE_BOOT_ALLOW_SHORT_APP_PARTITION AND
     endif()
 endif()
 
-if(CONFIG_ESP32_REV_MIN)
-    set(min_rev ${CONFIG_ESP32_REV_MIN})
+# We still set "--min-rev" to keep the app compatible with older booloaders where this field is controlled.
+if(CONFIG_IDF_TARGET_ESP32)
+    # for this chip min_rev is major revision
+    math(EXPR min_rev "${CONFIG_ESP_REV_MIN_FULL} / 100")
 endif()
-if(CONFIG_ESP32C3_REV_MIN)
-    set(min_rev ${CONFIG_ESP32C3_REV_MIN})
+if(CONFIG_IDF_TARGET_ESP32C3)
+    # for this chip min_rev is minor revision
+    math(EXPR min_rev "${CONFIG_ESP_REV_MIN_FULL} % 100")
 endif()
 
 if(min_rev)
     list(APPEND esptool_elf2image_args --min-rev ${min_rev})
-    set(monitor_rev_args "--revision;${min_rev}")
-    unset(min_rev)
 endif()
 
+list(APPEND esptool_elf2image_args --min-rev-full ${CONFIG_ESP_REV_MIN_FULL})
+list(APPEND esptool_elf2image_args --max-rev-full ${CONFIG_ESP_REV_MAX_FULL})
+
+set(monitor_rev_args "--revision;${CONFIG_ESP_REV_MIN_FULL}")
+
 if(CONFIG_ESPTOOLPY_FLASHSIZE_DETECT)
     # Set ESPFLASHSIZE to 'detect' *after* elf2image options are generated,
     # as elf2image can't have 'detect' as an option...
diff --git a/components/hal/efuse_hal.c b/components/hal/efuse_hal.c
index 061d1be89d2..133a81c4779 100644
--- a/components/hal/efuse_hal.c
+++ b/components/hal/efuse_hal.c
@@ -10,9 +10,10 @@
 #include "hal/efuse_ll.h"
 #include "hal/assert.h"
 #include "hal/efuse_hal.h"
+#include "esp_attr.h"
 
 
-uint32_t efuse_hal_chip_revision(void)
+IRAM_ATTR uint32_t efuse_hal_chip_revision(void)
 {
     return efuse_hal_get_major_chip_version() * 100 + efuse_hal_get_minor_chip_version();
 }
diff --git a/components/hal/esp32/efuse_hal.c b/components/hal/esp32/efuse_hal.c
index f0cfbfe9f5a..8cbae5200bc 100644
--- a/components/hal/esp32/efuse_hal.c
+++ b/components/hal/esp32/efuse_hal.c
@@ -11,8 +11,9 @@
 #include "hal/assert.h"
 #include "hal/efuse_hal.h"
 #include "soc/syscon_reg.h"
+#include "esp_attr.h"
 
-uint32_t efuse_hal_get_major_chip_version(void)
+IRAM_ATTR uint32_t efuse_hal_get_major_chip_version(void)
 {
     uint8_t eco_bit0 = efuse_ll_get_chip_ver_rev1();
     uint8_t eco_bit1 = efuse_ll_get_chip_ver_rev2();
@@ -44,7 +45,7 @@ uint32_t efuse_hal_get_major_chip_version(void)
     return chip_ver;
 }
 
-uint32_t efuse_hal_get_minor_chip_version(void)
+IRAM_ATTR uint32_t efuse_hal_get_minor_chip_version(void)
 {
     return efuse_ll_get_chip_wafer_version_minor();
 }
diff --git a/components/hal/esp32/include/hal/can_types.h b/components/hal/esp32/include/hal/can_types.h
index 4af81894f43..ba32ba549d0 100644
--- a/components/hal/esp32/include/hal/can_types.h
+++ b/components/hal/esp32/include/hal/can_types.h
@@ -38,7 +38,7 @@ extern "C" {
 #define CAN_MSG_FLAG_SELF               TWAI_MSG_FLAG_SELF
 #define CAN_MSG_FLAG_DLC_NON_COMP       TWAI_MSG_FLAG_DLC_NON_COMP
 
-#if (SOC_TWAI_BRP_MAX > 128) || (CONFIG_ESP32_REV_MIN >= 2)
+#if (SOC_TWAI_BRP_MAX > 128) || (CONFIG_ESP32_REV_MIN_FULL >= 200)
 #define CAN_TIMING_CONFIG_12_5KBITS()   TWAI_TIMING_CONFIG_12_5KBITS()
 #define CAN_TIMING_CONFIG_16KBITS()     TWAI_TIMING_CONFIG_16KBITS()
 #define CAN_TIMING_CONFIG_20KBITS()     TWAI_TIMING_CONFIG_20KBITS()
diff --git a/components/hal/esp32c3/efuse_hal.c b/components/hal/esp32c3/efuse_hal.c
index 9a8ff29492f..fd7cad29870 100644
--- a/components/hal/esp32c3/efuse_hal.c
+++ b/components/hal/esp32c3/efuse_hal.c
@@ -10,13 +10,14 @@
 #include "hal/assert.h"
 #include "hal/efuse_hal.h"
 #include "hal/efuse_ll.h"
+#include "esp_attr.h"
 
-uint32_t efuse_hal_get_major_chip_version(void)
+IRAM_ATTR uint32_t efuse_hal_get_major_chip_version(void)
 {
     return efuse_ll_get_chip_wafer_version_major();
 }
 
-uint32_t efuse_hal_get_minor_chip_version(void)
+IRAM_ATTR uint32_t efuse_hal_get_minor_chip_version(void)
 {
     return efuse_ll_get_chip_wafer_version_minor();
 }
diff --git a/components/hal/esp32h2/efuse_hal.c b/components/hal/esp32h2/efuse_hal.c
index 9a8ff29492f..fd7cad29870 100644
--- a/components/hal/esp32h2/efuse_hal.c
+++ b/components/hal/esp32h2/efuse_hal.c
@@ -10,13 +10,14 @@
 #include "hal/assert.h"
 #include "hal/efuse_hal.h"
 #include "hal/efuse_ll.h"
+#include "esp_attr.h"
 
-uint32_t efuse_hal_get_major_chip_version(void)
+IRAM_ATTR uint32_t efuse_hal_get_major_chip_version(void)
 {
     return efuse_ll_get_chip_wafer_version_major();
 }
 
-uint32_t efuse_hal_get_minor_chip_version(void)
+IRAM_ATTR uint32_t efuse_hal_get_minor_chip_version(void)
 {
     return efuse_ll_get_chip_wafer_version_minor();
 }
diff --git a/components/hal/esp32s2/efuse_hal.c b/components/hal/esp32s2/efuse_hal.c
index 9a8ff29492f..fd7cad29870 100644
--- a/components/hal/esp32s2/efuse_hal.c
+++ b/components/hal/esp32s2/efuse_hal.c
@@ -10,13 +10,14 @@
 #include "hal/assert.h"
 #include "hal/efuse_hal.h"
 #include "hal/efuse_ll.h"
+#include "esp_attr.h"
 
-uint32_t efuse_hal_get_major_chip_version(void)
+IRAM_ATTR uint32_t efuse_hal_get_major_chip_version(void)
 {
     return efuse_ll_get_chip_wafer_version_major();
 }
 
-uint32_t efuse_hal_get_minor_chip_version(void)
+IRAM_ATTR uint32_t efuse_hal_get_minor_chip_version(void)
 {
     return efuse_ll_get_chip_wafer_version_minor();
 }
diff --git a/components/hal/esp32s3/efuse_hal.c b/components/hal/esp32s3/efuse_hal.c
index 53f5a6ffd11..ace30d55f67 100644
--- a/components/hal/esp32s3/efuse_hal.c
+++ b/components/hal/esp32s3/efuse_hal.c
@@ -10,6 +10,7 @@
 #include "hal/assert.h"
 #include "hal/efuse_hal.h"
 #include "hal/efuse_ll.h"
+#include "esp_attr.h"
 
 #define ESP_EFUSE_BLOCK_ERROR_BITS(error_reg, block) ((error_reg) & (0x0F << (4 * (block))))
 
@@ -23,7 +24,7 @@ static inline bool is_eco0(uint32_t minor_raw)
             efuse_ll_get_blk_version_major() == 1 && efuse_ll_get_blk_version_minor() == 1);
 }
 
-uint32_t efuse_hal_get_major_chip_version(void)
+IRAM_ATTR uint32_t efuse_hal_get_major_chip_version(void)
 {
     uint32_t minor_raw = efuse_ll_get_chip_wafer_version_minor();
 
@@ -33,7 +34,7 @@ uint32_t efuse_hal_get_major_chip_version(void)
     return efuse_ll_get_chip_wafer_version_major();
 }
 
-uint32_t efuse_hal_get_minor_chip_version(void)
+IRAM_ATTR uint32_t efuse_hal_get_minor_chip_version(void)
 {
     uint32_t minor_raw = efuse_ll_get_chip_wafer_version_minor();
 
diff --git a/components/hal/include/hal/twai_types.h b/components/hal/include/hal/twai_types.h
index f4d5ef5286f..f7721dd4bf5 100644
--- a/components/hal/include/hal/twai_types.h
+++ b/components/hal/include/hal/twai_types.h
@@ -1,16 +1,8 @@
-// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 
 #pragma once
 
@@ -65,7 +57,7 @@ extern "C" {
 #define TWAI_TIMING_CONFIG_5KBITS()     {.brp = 800, .tseg_1 = 15, .tseg_2 = 4, .sjw = 3, .triple_sampling = false}
 #define TWAI_TIMING_CONFIG_10KBITS()    {.brp = 400, .tseg_1 = 15, .tseg_2 = 4, .sjw = 3, .triple_sampling = false}
 #endif
-#if (SOC_TWAI_BRP_MAX > 128) || (CONFIG_ESP32_REV_MIN >= 2)
+#if (SOC_TWAI_BRP_MAX > 128) || (CONFIG_ESP32_REV_MIN_FULL >= 200)
 #define TWAI_TIMING_CONFIG_12_5KBITS()  {.brp = 256, .tseg_1 = 16, .tseg_2 = 8, .sjw = 3, .triple_sampling = false}
 #define TWAI_TIMING_CONFIG_16KBITS()    {.brp = 200, .tseg_1 = 16, .tseg_2 = 8, .sjw = 3, .triple_sampling = false}
 #define TWAI_TIMING_CONFIG_20KBITS()    {.brp = 200, .tseg_1 = 15, .tseg_2 = 4, .sjw = 3, .triple_sampling = false}
diff --git a/components/soc/esp32/include/soc/soc_caps.h b/components/soc/esp32/include/soc/soc_caps.h
index e3d68c297ed..da51423424e 100644
--- a/components/soc/esp32/include/soc/soc_caps.h
+++ b/components/soc/esp32/include/soc/soc_caps.h
@@ -31,7 +31,7 @@
 #ifdef __has_include
 #  if __has_include("sdkconfig.h")
 #    include "sdkconfig.h"
-#    define SOC_CAPS_ECO_VER    CONFIG_ESP32_REV_MIN
+#    define SOC_CAPS_ECO_VER    CONFIG_ESP32_REV_MIN_FULL
 #  endif
 #endif
 
@@ -50,7 +50,7 @@
 #endif
 
 /*-------------------------- COMMON CAPS ---------------------------------------*/
-#define SOC_CAPS_ECO_VER_MAX        3
+#define SOC_CAPS_ECO_VER_MAX        301
 
 #define SOC_ADC_SUPPORTED           1
 #define SOC_DAC_SUPPORTED           1
@@ -102,7 +102,7 @@
 
 
 /*-------------------------- BROWNOUT CAPS -----------------------------------*/
-#if SOC_CAPS_ECO_VER >= 1
+#if SOC_CAPS_ECO_VER >= 100
 #define SOC_BROWNOUT_RESET_SUPPORTED 1
 #endif
 
@@ -252,7 +252,7 @@
 
 /*-------------------------- TWAI CAPS ---------------------------------------*/
 #define SOC_TWAI_BRP_MIN                        2
-#if SOC_CAPS_ECO_VER >= 2
+#if SOC_CAPS_ECO_VER >= 200
 #  define SOC_TWAI_BRP_MAX              256
 #  define SOC_TWAI_BRP_DIV_SUPPORTED    1
 #  define SOC_TWAI_BRP_DIV_THRESH       128
diff --git a/components/soc/include/soc/chip_revision.h b/components/soc/include/soc/chip_revision.h
new file mode 100644
index 00000000000..070de4918cd
--- /dev/null
+++ b/components/soc/include/soc/chip_revision.h
@@ -0,0 +1,40 @@
+/*
+ * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include "sdkconfig.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * Convenient macros to check current wafer version against a version where some changes are introduced.
+ * Use `ESP_CHIP_REV_ABOVE` for a change introduced before any major versions.
+ * Use `ESP_CHIP_REV_MAJOR_AND_ABOVE` for changes introduced after a major version is added.
+ * For example, on ESP32 we have wafer versions:
+ *
+ * 0.0 -> 1.0 -> 2.0 -> 3.0 -> 3.1 -> N.A.
+ *            |->1.1
+ *
+ * - If we are adding code for a change on 1.1, we should use `ESP_CHIP_REV_MAJOR_AND_ABOVE`
+ *   because there is already major version 2 existing. The condition will be met from 1.1 to 1.99,
+ *   while not inherited by 2.0 and above.
+ *
+ * - If we are adding code for a change on 3.1, we should use `ESP_CHIP_REV_ABOVE`
+ *   because there is no major version 4. The condition will be met from 3.1 to 3.99 and 4.0 and above.
+ *   Even if we add revision 4.0 on this version, the logic will be inherited.
+ */
+
+#define ESP_CHIP_REV_ABOVE(rev, min_rev) ((min_rev) <= (rev))
+#define ESP_CHIP_REV_MAJOR_AND_ABOVE(rev, min_rev) (((rev) / 100 == (min_rev) / 100) && ((rev) >= (min_rev)))
+
+_Static_assert(CONFIG_ESP_REV_MIN_FULL <= CONFIG_ESP_REV_MAX_FULL, "Min version must be less than Max version");
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/docs/doxygen/Doxyfile b/docs/doxygen/Doxyfile
index 859796b9e66..b277dadd323 100644
--- a/docs/doxygen/Doxyfile
+++ b/docs/doxygen/Doxyfile
@@ -112,6 +112,7 @@ INPUT = \
     $(PROJECT_PATH)/components/hal/include/hal/twai_types.h \
     $(PROJECT_PATH)/components/driver/include/driver/twai.h \
     $(PROJECT_PATH)/components/hal/include/hal/uart_types.h \
+    $(PROJECT_PATH)/components/hal/include/hal/efuse_hal.h \
     $(PROJECT_PATH)/components/soc/$(IDF_TARGET)/include/soc/uart_channel.h \
     $(PROJECT_PATH)/components/driver/include/driver/uart.h \
     $(PROJECT_PATH)/components/esp_netif/include/esp_netif.h \
diff --git a/docs/en/api-reference/system/chip_revision.rst b/docs/en/api-reference/system/chip_revision.rst
new file mode 100644
index 00000000000..8d6d4101dde
--- /dev/null
+++ b/docs/en/api-reference/system/chip_revision.rst
@@ -0,0 +1,129 @@
+Chip Revision
+=============
+
+Overview
+--------
+
+A new chip versioning logic was introduced in new chips. Chips have several eFuse version fields:
+
+- Major wafer version (``WAFER_VERSION_MAJOR`` eFuse)
+- Minor wafer version (``WAFER_VERSION_MINOR`` eFuse)
+- Ignore maximal revision (``DISABLE_WAFER_VERSION_MAJOR`` eFuse)
+
+The new versioning logic is being introduced to distinguish changes in chips as breaking changes and non-breaking changes. Chips with non-breaking changes can run the same software as the previous chip. The previous chip means that the major version is the same.
+
+If the newly released chip does not have breaking changes, that means it can run the same software as the previous chip, then in that chip we keep the same major version and increment the minor version by 1. Otherwise, if there is a breaking change in the newly released chip, meaning it can not run the same software as the previous chip, then in that chip we increase the major version and set the minor version to 0.
+
+The software supports a number of revisions, from the minimum to the maximum (the min/max configs are defined in Kconfig). If the software is unaware of a new chip (when the chip version is out of range), it will refuse to run on it unless the Ignore maximum revision restrictions bit is set. This bit removes the upper revision limit.
+
+Minimum versions limits the software to only run on a chip revision that is high enough to support some features. Maximum version is the maximum version that is well-supported by current software. When chip version is above the maximum version, software will reject to boot, because it may not work on, or work with risk on the chip.
+
+Adding the major and minor wafer revision make the versioning logic is branchable.
+
+.. note::
+
+    The previous versioning logic was based on a single eFuse version field (``WAFER_VERSION``). This approach makes it impossible to mark chips as breaking or non-breaking changes, and the versioning logic becomes linear.
+
+Using the branched versioning scheme allows us to support more chips in the software without updating the software when a new released compatible chip is used. Thus, the software will be compatible with as many new chip revisions as possible. If the software is no longer compatible with a new chip with breaking changes, the software will abort.
+
+Revisions
+---------
+
+.. include:: inc/revisions_{IDF_TARGET_NAME}.rst
+
+Chip Revision ``vX.Y``, where:
+
+- ``X`` means Major wafer version. If it is changed, it means that the current software version is not compatible with this released chip and the software must be updated to use this chip.
+- ``Y`` means Minor wafer version. If it is changed that means the current software version is compatible with the released chip, and there is no need to update the software.
+
+The ``vX.Y`` chip version format will be used further instead of the ECO number.
+
+Representing Revision Requirement Of A Binary Image
+---------------------------------------------------
+
+The 2nd stage bootloader and the application binary images have the :cpp:type:`esp_image_header_t` header, which stores the revision numbers of the chip on which the software can be run. This header has 3 fields related to revisions:
+
+- ``min_chip_rev`` - Minimal chip MAJOR revision required by image (but for ESP32-C3 it is MINOR revision). Its value is determined by :ref:`CONFIG_{IDF_TARGET_CFG_PREFIX}_REV_MIN`.
+- ``min_chip_rev_full`` - Minimal chip MINOR revision required by image in format: ``major * 100 + minor``. Its value is determined by :ref:`CONFIG_{IDF_TARGET_CFG_PREFIX}_REV_MIN`.
+- ``max_chip_rev_full`` - Maximal chip revision required by image in format: ``major * 100 + minor``. Its value is determined by ``CONFIG_{IDF_TARGET_CFG_PREFIX}_REV_MAX_FULL``. It can not be changed by user. Only Espressif can change it when a new version will be supported in IDF.
+
+Chip Revision APIs
+------------------
+
+These APIs helps to get chip revision from eFuses:
+
+- :cpp:func:`efuse_hal_chip_revision`. It returns revision in the ``major * 100 + minor`` format.
+- :cpp:func:`efuse_hal_get_major_chip_version`. It returns Major revision.
+- :cpp:func:`efuse_hal_get_minor_chip_version`. It returns Minor revision.
+
+The following Kconfig definitions (in ``major * 100 + minor`` format) that can help add the chip revision dependency to the code:
+
+- ``CONFIG_{IDF_TARGET_CFG_PREFIX}_REV_MIN_FULL``
+- ``CONFIG_ESP_REV_MIN_FULL``
+- ``CONFIG_{IDF_TARGET_CFG_PREFIX}_REV_MAX_FULL``
+- ``CONFIG_ESP_REV_MAX_FULL``
+
+Maximal And Minimal Revision Restrictions
+-----------------------------------------
+
+The order for checking the minimum and maximum revisions:
+
+1. The 1st stage bootloader (ROM bootloader) does not check minimal and maximal revision fields from :cpp:type:`esp_image_header_t` before running the 2nd stage bootloader.
+
+2. The 2nd stage bootloader checks at the initialization phase that bootloader itself can be launched on the chip of this revision. It extracts the minimum revision from the header of the bootloader image and checks against the chip revision from eFuses. If the chip revision is less than the minimum revision, the bootloader refuses to boot up and aborts. The maximum revision is not checked at this phase.
+
+3. Then the 2nd stage bootloader checks the revision requirements of the application. It extracts the minimum and maximum revisions from the header of the application image and checks against the chip revision from eFuses. If the chip revision is less than the minimum revision or higher than the maximum revision, the bootloader refuses to boot up and aborts. However, if the Ignore maximal revision bit is set, the maximum revision constraint can be ignored. The ignore bit is set by the customer themself when there is confirmation that the software is able to work with this chip revision.
+
+4. Further, at the OTA update stage, the running application checks if the new software matches the chip revision. It extracts the minimum and maximum revisions from the header of the new application image and checks against the chip revision from eFuses. It checks for revision matching in the same way that the bootloader does, so that the chip revision is between the min and max revisions (logic of ignoring max revision also applies).
+
+Issues
+------
+
+1. If the 2nd stage bootloader is run on the chip revision < minimum revision shown in the image, a reboot occurs. The following message will be printed:
+
+.. code-block:: none
+
+    Image requires chip rev >= v3.0, but chip is v1.0
+
+To resolve this issue:
+
+- make sure the chip you are using is suitable for the software, or use a chip with the required minimum revision or higher.
+- update the software with :ref:`CONFIG_{IDF_TARGET_CFG_PREFIX}_REV_MIN` to get it ``<=`` the revision of chip being used
+
+2. If application does not match minimal and maximal chip revisions, a reboot occurs. The following message will be printed:
+
+.. code-block:: none
+
+    Image requires chip rev <= v2.99, but chip is v3.0
+
+To resolve this issue, update the IDF to a newer version that supports the used chip (``CONFIG_{IDF_TARGET_CFG_PREFIX}_REV_MAX_FULL``). Another way to fix this is to set the ``Ignore maximal revision`` bit in eFuse or use a chip that is suitable for the software.
+
+Backward Compatible With Bootloaders Built By Older ESP-IDF Versions
+--------------------------------------------------------------------
+
+.. only:: esp32 or esp32c3 or esp32s2 or esp32s3
+
+    The old bootloaders (IDF < 5.0) do not know about Major and Minor wafer version eFuses. They use one single eFuse for this - wafer version.
+
+.. only:: esp32
+
+    The old bootloaders did not read the minor wafer version eFuse, the major version can be only <= 3. So it means that the old bootloader can detect correctly only chip version in range v0.0 - v3.0, where the minor version is always 0.
+
+.. only:: esp32c2
+
+    {IDF_TARGET_NAME} chip support was added in IDF 5.0. The bootloader is able to detect any chip versions in range v0.0 - v3.15.
+
+.. only:: esp32c3
+
+    {IDF_TARGET_NAME} chip support was added in IDF 4.3. The old bootloaders can not read all bits of the wafer version eFuse, it can read only the first 3 low bits. So it means that the old bootloader can not detect chip version correctly. Chips v0.0 - v0.8 will be detected correctly, but other chip versions will be recognized as a version from this range.
+
+.. only:: esp32s2 or esp32s3
+
+    {IDF_TARGET_NAME} chip support was added in IDF 4.2. {IDF_TARGET_NAME} chips have ``rev_min`` in :cpp:type:`esp_image_header_t` header = 0 because ``Minimum Supported ESP32-S2 Revision`` Kconfig option was not introduced, it means that the old bootloader does not check the chip revision. Any app can be loaded by such bootloader in range v0.0 - v3.15.
+
+Please check the chip version using ``esptool chip_id`` command.
+
+API Reference
+-------------
+
+.. include-build-file:: inc/efuse_hal.inc
diff --git a/docs/en/api-reference/system/inc/revisions_ESP32-C3.rst b/docs/en/api-reference/system/inc/revisions_ESP32-C3.rst
new file mode 100644
index 00000000000..2f5630b1add
--- /dev/null
+++ b/docs/en/api-reference/system/inc/revisions_ESP32-C3.rst
@@ -0,0 +1,12 @@
+
++--------+------------------------+
+| ECO    | Revision (Major.Minor) |
++--------+------------------------+
+| ECO1   | v0.1                   |
++--------+------------------------+
+| ECO2   | v0.2                   |
++--------+------------------------+
+| ECO3   | v0.3                   |
++--------+------------------------+
+| ECO4   | v0.4                   |
++--------+------------------------+
diff --git a/docs/en/api-reference/system/inc/revisions_ESP32-S2.rst b/docs/en/api-reference/system/inc/revisions_ESP32-S2.rst
new file mode 100644
index 00000000000..afc2fd488bb
--- /dev/null
+++ b/docs/en/api-reference/system/inc/revisions_ESP32-S2.rst
@@ -0,0 +1,8 @@
+
++--------+------------------------+
+| ECO    | Revision (Major.Minor) |
++--------+------------------------+
+| ECO0   | v0.0                   |
++--------+------------------------+
+| ECO1   | v1.0                   |
++--------+------------------------+
diff --git a/docs/en/api-reference/system/inc/revisions_ESP32-S3.rst b/docs/en/api-reference/system/inc/revisions_ESP32-S3.rst
new file mode 100644
index 00000000000..7bb4949df1b
--- /dev/null
+++ b/docs/en/api-reference/system/inc/revisions_ESP32-S3.rst
@@ -0,0 +1,10 @@
+
++--------+------------------------+
+| ECO    | Revision (Major.Minor) |
++--------+------------------------+
+| ECO0   | v0.0                   |
++--------+------------------------+
+| ECO1   | v0.1                   |
++--------+------------------------+
+| ECO2   | v0.2                   |
++--------+------------------------+
diff --git a/docs/en/api-reference/system/inc/revisions_ESP32.rst b/docs/en/api-reference/system/inc/revisions_ESP32.rst
new file mode 100644
index 00000000000..b729ef5a644
--- /dev/null
+++ b/docs/en/api-reference/system/inc/revisions_ESP32.rst
@@ -0,0 +1,16 @@
+
++--------+------------------------+
+| ECO    | Revision (Major.Minor) |
++--------+------------------------+
+| ECO0   | v0.0                   |
++--------+------------------------+
+| ECO1   | v1.0                   |
++--------+------------------------+
+| ECO1.1 | v1.1                   |
++--------+------------------------+
+| ECO2   | v2.0                   |
++--------+------------------------+
+| ECO3   | v3.0                   |
++--------+------------------------+
+| ECO4   | v3.1                   |
++--------+------------------------+
diff --git a/docs/en/api-reference/system/index.rst b/docs/en/api-reference/system/index.rst
index adc4a2930ef..db804b879b9 100644
--- a/docs/en/api-reference/system/index.rst
+++ b/docs/en/api-reference/system/index.rst
@@ -7,6 +7,7 @@ System API
     App image format <app_image_format>
     Application Level Tracing <app_trace>
     :SOC_ASYNC_MEMCPY_SUPPORTED: Async Memory Copy <async_memcpy>
+    Chip Revision <chip_revision>
     Console Component <console>
     eFuse Manager <efuse>
     Error Codes and Helper Functions <esp_err>
diff --git a/docs/zh_CN/api-reference/system/chip_revision.rst b/docs/zh_CN/api-reference/system/chip_revision.rst
new file mode 100644
index 00000000000..71903a0dfd7
--- /dev/null
+++ b/docs/zh_CN/api-reference/system/chip_revision.rst
@@ -0,0 +1 @@
+.. include:: ../../../en/api-reference/system/chip_revision.rst
diff --git a/docs/zh_CN/api-reference/system/inc/revisions_ESP32-C3.rst b/docs/zh_CN/api-reference/system/inc/revisions_ESP32-C3.rst
new file mode 100644
index 00000000000..a02582a1517
--- /dev/null
+++ b/docs/zh_CN/api-reference/system/inc/revisions_ESP32-C3.rst
@@ -0,0 +1 @@
+.. include:: ../../../en/api-reference/system/inc/revisions_ESP32-C3.rst
diff --git a/docs/zh_CN/api-reference/system/inc/revisions_ESP32-S2.rst b/docs/zh_CN/api-reference/system/inc/revisions_ESP32-S2.rst
new file mode 100644
index 00000000000..4ca30773ef9
--- /dev/null
+++ b/docs/zh_CN/api-reference/system/inc/revisions_ESP32-S2.rst
@@ -0,0 +1 @@
+.. include:: ../../../en/api-reference/system/inc/revisions_ESP32-S2.rst
diff --git a/docs/zh_CN/api-reference/system/inc/revisions_ESP32-S3.rst b/docs/zh_CN/api-reference/system/inc/revisions_ESP32-S3.rst
new file mode 100644
index 00000000000..6690aa320bd
--- /dev/null
+++ b/docs/zh_CN/api-reference/system/inc/revisions_ESP32-S3.rst
@@ -0,0 +1 @@
+.. include:: ../../../en/api-reference/system/inc/revisions_ESP32-S3.rst
diff --git a/docs/zh_CN/api-reference/system/inc/revisions_ESP32.rst b/docs/zh_CN/api-reference/system/inc/revisions_ESP32.rst
new file mode 100644
index 00000000000..fb4822a8340
--- /dev/null
+++ b/docs/zh_CN/api-reference/system/inc/revisions_ESP32.rst
@@ -0,0 +1 @@
+.. include:: ../../../en/api-reference/system/inc/revisions_ESP32.rst
diff --git a/docs/zh_CN/api-reference/system/index.rst b/docs/zh_CN/api-reference/system/index.rst
index cdf03b734da..aa80bfdef70 100644
--- a/docs/zh_CN/api-reference/system/index.rst
+++ b/docs/zh_CN/api-reference/system/index.rst
@@ -1 +1 @@
-.. include:: ../../../en/api-reference/system/index.rst
\ No newline at end of file
+.. include:: ../../../en/api-reference/system/index.rst
diff --git a/examples/bluetooth/nimble/throughput_app/blecent_throughput/components/cmd_system/cmd_system.c b/examples/bluetooth/nimble/throughput_app/blecent_throughput/components/cmd_system/cmd_system.c
index 4fa3240b1cd..7351d2c7537 100644
--- a/examples/bluetooth/nimble/throughput_app/blecent_throughput/components/cmd_system/cmd_system.c
+++ b/examples/bluetooth/nimble/throughput_app/blecent_throughput/components/cmd_system/cmd_system.c
@@ -64,7 +64,9 @@ static int get_version(int argc, char **argv)
            info.features & CHIP_FEATURE_BT ? "/BT" : "",
            info.features & CHIP_FEATURE_EMB_FLASH ? "/Embedded-Flash:" : "/External-Flash:",
            spi_flash_get_chip_size() / (1024 * 1024), " MB");
-    printf("\trevision number:%d\r\n", info.revision);
+    unsigned major_rev = info.full_revision / 100;
+    unsigned minor_rev = info.full_revision % 100;
+    printf("\trevision number:v%d.%d\r\n", major_rev, minor_rev);
     return 0;
 }
 
diff --git a/examples/build_system/cmake/idf_as_lib/main.c b/examples/build_system/cmake/idf_as_lib/main.c
index 9eb73f55ef8..f1f6c96e16d 100644
--- a/examples/build_system/cmake/idf_as_lib/main.c
+++ b/examples/build_system/cmake/idf_as_lib/main.c
@@ -24,7 +24,9 @@ void app_main(void)
             (chip_info.features & CHIP_FEATURE_BT) ? "/BT" : "",
             (chip_info.features & CHIP_FEATURE_BLE) ? "/BLE" : "");
 
-    printf("silicon revision %d, ", chip_info.revision);
+    unsigned major_rev = chip_info.full_revision / 100;
+    unsigned minor_rev = chip_info.full_revision % 100;
+    printf("silicon revision v%d.%d, ", major_rev, minor_rev);
 
     printf("%dMB %s flash\n", spi_flash_get_chip_size() / (1024 * 1024),
             (chip_info.features & CHIP_FEATURE_EMB_FLASH) ? "embedded" : "external");
diff --git a/examples/get-started/hello_world/main/hello_world_main.c b/examples/get-started/hello_world/main/hello_world_main.c
index ebc5eb0b048..b38d9b7ae88 100644
--- a/examples/get-started/hello_world/main/hello_world_main.c
+++ b/examples/get-started/hello_world/main/hello_world_main.c
@@ -26,7 +26,9 @@ void app_main(void)
             (chip_info.features & CHIP_FEATURE_BT) ? "/BT" : "",
             (chip_info.features & CHIP_FEATURE_BLE) ? "/BLE" : "");
 
-    printf("silicon revision %d, ", chip_info.revision);
+    unsigned major_rev = chip_info.full_revision / 100;
+    unsigned minor_rev = chip_info.full_revision % 100;
+    printf("silicon revision v%d.%d, ", major_rev, minor_rev);
 
     printf("%dMB %s flash\n", spi_flash_get_chip_size() / (1024 * 1024),
             (chip_info.features & CHIP_FEATURE_EMB_FLASH) ? "embedded" : "external");
diff --git a/examples/security/flash_encryption/main/flash_encrypt_main.c b/examples/security/flash_encryption/main/flash_encrypt_main.c
index fad5debd7bf..fce46038556 100644
--- a/examples/security/flash_encryption/main/flash_encrypt_main.c
+++ b/examples/security/flash_encryption/main/flash_encrypt_main.c
@@ -60,7 +60,9 @@ static void example_print_chip_info(void)
             (chip_info.features & CHIP_FEATURE_BT) ? "/BT" : "",
             (chip_info.features & CHIP_FEATURE_BLE) ? "/BLE" : "");
 
-    printf("silicon revision %d, ", chip_info.revision);
+    unsigned major_rev = chip_info.full_revision / 100;
+    unsigned minor_rev = chip_info.full_revision % 100;
+    printf("silicon revision v%d.%d, ", major_rev, minor_rev);
 
     printf("%dMB %s flash\n", spi_flash_get_chip_size() / (1024 * 1024),
             (chip_info.features & CHIP_FEATURE_EMB_FLASH) ? "embedded" : "external");
diff --git a/examples/system/console/advanced/components/cmd_system/cmd_system.c b/examples/system/console/advanced/components/cmd_system/cmd_system.c
index 6e82c3df9a0..7ed89012cec 100644
--- a/examples/system/console/advanced/components/cmd_system/cmd_system.c
+++ b/examples/system/console/advanced/components/cmd_system/cmd_system.c
@@ -78,7 +78,9 @@ static int get_version(int argc, char **argv)
            info.features & CHIP_FEATURE_BT ? "/BT" : "",
            info.features & CHIP_FEATURE_EMB_FLASH ? "/Embedded-Flash:" : "/External-Flash:",
            spi_flash_get_chip_size() / (1024 * 1024), " MB");
-    printf("\trevision number:%d\r\n", info.revision);
+    unsigned major_rev = info.full_revision / 100;
+    unsigned minor_rev = info.full_revision % 100;
+    printf("\trevision number:v%d.%d\r\n", major_rev, minor_rev);
     return 0;
 }
 
diff --git a/tools/cmake/project_description.json.in b/tools/cmake/project_description.json.in
index db18650e45a..d3707eb9cc2 100644
--- a/tools/cmake/project_description.json.in
+++ b/tools/cmake/project_description.json.in
@@ -9,6 +9,8 @@
     "git_revision":       "${IDF_VER}",
     "target":             "${CONFIG_IDF_TARGET}",
     "rev":                "${CONFIG_ESP32_REV_MIN}",
+    "min_rev":            "${CONFIG_ESP_REV_MIN_FULL}",
+    "max_rev":            "${CONFIG_ESP_REV_MAX_FULL}",
     "phy_data_partition": "${CONFIG_ESP32_PHY_INIT_DATA_IN_PARTITION}",
     "monitor_baud" :      "${CONFIG_ESPTOOLPY_MONITOR_BAUD}",
     "monitor_toolprefix": "${CONFIG_SDK_TOOLPREFIX}",
diff --git a/tools/idf_monitor_base/chip_specific_config.py b/tools/idf_monitor_base/chip_specific_config.py
index fa207c5bdc5..50dd3232737 100644
--- a/tools/idf_monitor_base/chip_specific_config.py
+++ b/tools/idf_monitor_base/chip_specific_config.py
@@ -38,7 +38,7 @@
             'enter_boot_set': 1.3,
             'enter_boot_unset': 0.45,
         },
-        1: {
+        100: {
             'reset': 0.2,
             'enter_boot_set': 0.1,
             'enter_boot_unset': 0.05,
diff --git a/tools/test_apps/security/secure_boot/main/secure_boot_main.c b/tools/test_apps/security/secure_boot/main/secure_boot_main.c
index 0ca31e3bfa9..b8b64a0ad8f 100644
--- a/tools/test_apps/security/secure_boot/main/secure_boot_main.c
+++ b/tools/test_apps/security/secure_boot/main/secure_boot_main.c
@@ -39,7 +39,9 @@ static void example_print_chip_info(void)
     esp_chip_info(&chip_info);
     printf("This is %s chip with %d CPU cores\n", CONFIG_IDF_TARGET, chip_info.cores);
 
-    printf("silicon revision %d, ", chip_info.revision);
+    unsigned major_rev = chip_info.full_revision / 100;
+    unsigned minor_rev = chip_info.full_revision % 100;
+    printf("silicon revision v%d.%d, ", major_rev, minor_rev);
 
     printf("%dMB %s flash\n", spi_flash_get_chip_size() / (1024 * 1024),
             (chip_info.features & CHIP_FEATURE_EMB_FLASH) ? "embedded" : "external");
diff --git a/tools/test_apps/security/secure_boot/main/secure_boot_main_esp32.c b/tools/test_apps/security/secure_boot/main/secure_boot_main_esp32.c
index 75328d97174..ad47304b3b9 100644
--- a/tools/test_apps/security/secure_boot/main/secure_boot_main_esp32.c
+++ b/tools/test_apps/security/secure_boot/main/secure_boot_main_esp32.c
@@ -41,7 +41,9 @@ static void example_print_chip_info(void)
             (chip_info.features & CHIP_FEATURE_BT) ? "/BT" : "",
             (chip_info.features & CHIP_FEATURE_BLE) ? "/BLE" : "");
 
-    printf("silicon revision %d, ", chip_info.revision);
+    unsigned major_rev = chip_info.full_revision / 100;
+    unsigned minor_rev = chip_info.full_revision % 100;
+    printf("silicon revision v%d.%d, ", major_rev, minor_rev);
 
     printf("%dMB %s flash\n", spi_flash_get_chip_size() / (1024 * 1024),
             (chip_info.features & CHIP_FEATURE_EMB_FLASH) ? "embedded" : "external");
@@ -53,7 +55,7 @@ static void example_secure_boot_status(void)
 {
     uint32_t efuse_block0 = REG_READ(EFUSE_BLK0_RDATA6_REG);
 
-#ifdef CONFIG_ESP32_REV_MIN_3
+#if CONFIG_ESP32_REV_MIN_FULL >= 300
     uint8_t efuse_trusted_digest[DIGEST_LEN] = {0}, i;
     ESP_LOGI(TAG, "Checking for secure boot v2..");
     if(efuse_block0 & EFUSE_RD_ABS_DONE_1) {
@@ -72,9 +74,9 @@ static void example_secure_boot_status(void)
     ESP_LOGI(TAG, "Checking for secure boot v1..");
     uint32_t dis_reg = REG_READ(EFUSE_BLK0_RDATA0_REG);
     if (efuse_block0 & EFUSE_RD_ABS_DONE_0) {
-    ESP_LOGI(TAG, "ABS_DONE_0 is set. Secure Boot V1 enabled");
-#ifdef CONFIG_ESP32_REV_MIN_3
-    ESP_LOGW(TAG, "This chip version supports Secure Boot V2. It is recommended to use Secure Boot V2.");
+        ESP_LOGI(TAG, "ABS_DONE_0 is set. Secure Boot V1 enabled");
+#if CONFIG_ESP32_REV_MIN_FULL >= 300
+        ESP_LOGW(TAG, "This chip version supports Secure Boot V2. It is recommended to use Secure Boot V2.");
 #endif
         bool efuse_key_read_protected = dis_reg & EFUSE_RD_DIS_BLK2;
         bool efuse_key_write_protected = dis_reg & EFUSE_WR_DIS_BLK2;
diff --git a/tools/test_apps/system/gdb_loadable_elf/main/hello_world_main.c b/tools/test_apps/system/gdb_loadable_elf/main/hello_world_main.c
index 1bbb227906b..e2c7e96722d 100644
--- a/tools/test_apps/system/gdb_loadable_elf/main/hello_world_main.c
+++ b/tools/test_apps/system/gdb_loadable_elf/main/hello_world_main.c
@@ -26,7 +26,9 @@ void app_main(void)
             (chip_info.features & CHIP_FEATURE_BT) ? "/BT" : "",
             (chip_info.features & CHIP_FEATURE_BLE) ? "/BLE" : "");
 
-    printf("silicon revision %d, ", chip_info.revision);
+    unsigned major_rev = chip_info.full_revision / 100;
+    unsigned minor_rev = chip_info.full_revision % 100;
+    printf("silicon revision v%d.%d, ", major_rev, minor_rev);
 
     printf("%dMB %s flash\n", spi_flash_get_chip_size() / (1024 * 1024),
             (chip_info.features & CHIP_FEATURE_EMB_FLASH) ? "embedded" : "external");