Detect Wires that don't get unioned with anything in Yosys plugin

[gussmith23]

We generate Wires for every node in the Verilog program, and in theory, each should get unioned with something. If a Wire doesn't get unioned with anything and then is deleted, we end up with an empty eclass. We should be able to detect when we haven't unioned a Wire with anything by keeping a map from created Wires to a boolean or count of unions.