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Properly connect reset and cs signals
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Starting to get (corrupt) data out of the memory...
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Raptor Engineering Development Team committed Apr 7, 2022
1 parent 6b41f65 commit ca3e97f
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Showing 5 changed files with 72 additions and 19 deletions.
8 changes: 5 additions & 3 deletions examples/headless-versa-85.py
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Original file line number Diff line number Diff line change
Expand Up @@ -19,7 +19,8 @@
from gram.frontend.wishbone import gramWishbone

from nmigen_boards.versa_ecp5 import VersaECP5Platform85
from ecp5_crg import ECP5CRG
#from ecp5_crg import ECP5CRG
from crg import ECPIX5CRG
from uartbridge import UARTBridge
from crg import *

Expand All @@ -30,12 +31,13 @@ def __init__(self, *,
self._decoder = wishbone.Decoder(addr_width=30, data_width=32, granularity=8,
features={"cti", "bte"})

self.crg = ECP5CRG()
self.crg = ECPIX5CRG()
#self.crg = ECP5CRG()

self.ub = UARTBridge(divisor=868, pins=platform.request("uart", 0))

ddr_pins = platform.request("ddr3", 0, dir={"dq":"-", "dqs":"-"},
xdr={"clk":4, "a":4, "ba":4, "clk_en":4, "odt":4, "ras":4, "cas":4, "we":4, "cs":4, "reset":4})
xdr={"clk":4, "a":4, "ba":4, "clk_en":4, "odt":4, "ras":4, "cas":4, "we":4, "cs":4, "rst":1})
self.ddrphy = DomainRenamer("dramsync")(ECP5DDRPHY(ddr_pins))
self._decoder.add(self.ddrphy.bus, addr=ddrphy_addr)

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37 changes: 34 additions & 3 deletions examples/headless/main.c
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Original file line number Diff line number Diff line change
Expand Up @@ -110,16 +110,25 @@ int main(int argc, char *argv[]) {

uint32_t ddr_base = 0x10000000;

#if 1
#if 0
struct gramProfile profile = {
.mode_registers = {
0x2708, 0x2054, 0x0512, 0x0000
0xb30, 0x806, 0x200, 0x0
},
.rdly_p0 = 2,
.rdly_p1 = 2,
};
#endif
#if 0
struct gramProfile profile = {
.mode_registers = {
0xb20, 0x806, 0x200, 0x0
},
.rdly_p0 = 2,
.rdly_p1 = 2,
};
#endif
#if 1
struct gramProfile profile = {
.mode_registers = {
0x320, 0x6, 0x200, 0x0
Expand Down Expand Up @@ -149,6 +158,7 @@ int main(int argc, char *argv[]) {
gram_init(&ctx, &profile, (void*)ddr_base, (void*)0x00009000, (void*)0x00008000);
printf("done\n");

#if 0
printf("Rdly\np0: ");
for (size_t i = 0; i < 8; i++) {
profile2.rdly_p0 = i;
Expand Down Expand Up @@ -198,6 +208,7 @@ int main(int argc, char *argv[]) {
printf("\tp1 rdly: %d\n", profile2.rdly_p1);

gram_reset_burstdet(&ctx);
#endif

srand(time(NULL));
for (i = 0; i < kPatternSize; i++) {
Expand All @@ -220,6 +231,26 @@ int main(int argc, char *argv[]) {
printf("done\n");
}

printf("Dumping data sequence...\n");
for (i = 0; i < kPatternSize; i++) {
if ((i % kDumpWidth) == 0) {
printf("%08x | ", ddr_base+4*i);
}

expected_value = pattern[i];

for (int j = 3; j >= 0; j--) {
printf("%02x", ((uint8_t*)(&expected_value))[j]);
}

if ((i % kDumpWidth) == kDumpWidth-1) {
printf("\n");
} else {
printf(" ");
}
}
printf("\n");

printf("Reading data sequence...\n");
for (i = 0; i < kPatternSize; i++) {
if ((i % kDumpWidth) == 0) {
Expand All @@ -237,7 +268,7 @@ int main(int argc, char *argv[]) {
printf("\033[0;32m%02x\033[0m", ((uint8_t*)(&read_value))[j]);
}
}

if ((i % kDumpWidth) == kDumpWidth-1) {
printf("\n");
} else {
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2 changes: 1 addition & 1 deletion gram/phy/dfi.py
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Original file line number Diff line number Diff line change
Expand Up @@ -47,7 +47,7 @@ def __init__(self, addressbits, bankbits, nranks, databits, nphases=1,
p.cas.reset = 1
p.ras.reset = 1
p.reset.reset = 1
p.cs_n.reset = -1
p.cs_n.reset = 1
p.we.reset = 1
p.act.reset = 1

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38 changes: 29 additions & 9 deletions gram/phy/ecp5ddrphy.py
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Original file line number Diff line number Diff line change
Expand Up @@ -253,17 +253,37 @@ def elaborate(self, platform):
# dfi.Interface it is "reset"
dfi2pads = {'rst': 'reset', 'cs': 'cs_n'}
name = dfi2pads.get(name, name) # remap if exists
m.d.comb += [
pad.o_clk.eq(ClockSignal("dramsync")),
pad.o_fclk.eq(ClockSignal("sync2x")),
]
for i in range(len(pad.o0)):
if name == "reset":
m.d.comb += [
pad.o_clk.eq(ClockSignal("sync")),
]
else:
m.d.comb += [
pad.o0[i].eq(getattr(dfi.phases[0], name)[i]),
pad.o1[i].eq(getattr(dfi.phases[0], name)[i]),
pad.o2[i].eq(getattr(dfi.phases[1], name)[i]),
pad.o3[i].eq(getattr(dfi.phases[1], name)[i]),
pad.o_clk.eq(ClockSignal("dramsync")),
pad.o_fclk.eq(ClockSignal("sync2x")),
]
if name == "reset":
for i in range(len(pad.o)):
m.d.comb += [
pad.o[i].eq(getattr(dfi.phases[0], name)[i]),
]
elif name == "cs_n":
# cs_n can't be directly connected to cs without being inverted first...
for i in range(len(pad.o0)):
m.d.comb += [
pad.o0[i].eq(~getattr(dfi.phases[0], name)[i]),
pad.o1[i].eq(~getattr(dfi.phases[0], name)[i]),
pad.o2[i].eq(~getattr(dfi.phases[1], name)[i]),
pad.o3[i].eq(~getattr(dfi.phases[1], name)[i]),
]
else:
for i in range(len(pad.o0)):
m.d.comb += [
pad.o0[i].eq(getattr(dfi.phases[0], name)[i]),
pad.o1[i].eq(getattr(dfi.phases[0], name)[i]),
pad.o2[i].eq(getattr(dfi.phases[1], name)[i]),
pad.o3[i].eq(getattr(dfi.phases[1], name)[i]),
]

# DQ ---------------------------------------------------------------------------------------
dq_oe = Signal()
Expand Down
6 changes: 3 additions & 3 deletions libgram/src/dfii.c
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Original file line number Diff line number Diff line change
Expand Up @@ -15,7 +15,7 @@ static void dfii_setcontrol(const struct gramCtx *ctx, uint8_t val) {

void dfii_setsw(const struct gramCtx *ctx, bool software_control) {
if (software_control) {
dfii_setcontrol(ctx, DFII_CONTROL_CKE|DFII_CONTROL_ODT);
dfii_setcontrol(ctx, DFII_CONTROL_CKE|DFII_CONTROL_ODT|DFII_CONTROL_RESET|DFII_COMMAND_CS);
} else {
dfii_setcontrol(ctx, DFII_CONTROL_SEL|DFII_CONTROL_RESET);
}
Expand Down Expand Up @@ -59,13 +59,13 @@ void dfii_initseq(const struct gramCtx *ctx, const struct gramProfile *profile)
/* Release reset */
dfii_set_p0_address(ctx, 0x0);
dfii_set_p0_baddress(ctx, 0);
dfii_setcontrol(ctx, DFII_CONTROL_ODT);
dfii_setcontrol(ctx, DFII_CONTROL_ODT|DFII_CONTROL_RESET);
cdelay(50000);

/* Bring CKE high */
dfii_set_p0_address(ctx, 0x0);
dfii_set_p0_baddress(ctx, 0);
dfii_setcontrol(ctx, DFII_CONTROL_CKE|DFII_CONTROL_ODT);
dfii_setcontrol(ctx, DFII_CONTROL_CKE|DFII_CONTROL_ODT|DFII_CONTROL_RESET);
cdelay(10000);

/* Load Mode Register 2, CWL=5 */
Expand Down

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