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Implement full mtval #2929

Implement full mtval

Implement full mtval #2929

Triggered via pull request September 21, 2024 11:41
Status Success
Total duration 14m 0s
Artifacts 1

main.yml

on: pull_request
Synthesize full core
59s
Synthesize full core
Build regression tests (riscv-tests)
46s
Build regression tests (riscv-tests)
Build regression tests (riscv-arch-test)
45s
Build regression tests (riscv-arch-test)
Run unit tests
8m 13s
Run unit tests
Check code formatting and typing
54s
Check code formatting and typing
Run regression tests (riscv-tests)
3m 51s
Run regression tests (riscv-tests)
Run regression tests (riscv-arch-test)
12m 43s
Run regression tests (riscv-arch-test)
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Artifacts

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Name Size
verilog-full-core
460 KB