Skip to content

Commit

Permalink
Autumn cleaning part 2 - split transactron/lib.py (#464)
Browse files Browse the repository at this point in the history
  • Loading branch information
@tilk
tilk committed Oct 7, 2023
1 parent be4baaa commit cd0a0c0
Show file tree
Hide file tree
Showing 44 changed files with 1,378 additions and 928 deletions.
Binary file modified .doctrees/Current_graph.doctree
View file
Binary file not shown.
Binary file modified .doctrees/api.doctree
View file
Binary file not shown.
Binary file modified .doctrees/auto_graph.doctree
View file
Binary file not shown.
Binary file modified .doctrees/coreblocks.params.doctree
View file
Binary file not shown.
Binary file modified .doctrees/environment.pickle
View file
Binary file not shown.
Binary file modified .doctrees/transactron.doctree
View file
Binary file not shown.
Binary file added .doctrees/transactron.lib.doctree
View file
Binary file not shown.
2 changes: 1 addition & 1 deletion Assumptions.html
View file
Original file line number Diff line number Diff line change
Expand Up @@ -104,7 +104,7 @@ <h1>List of assumptions made during development<a class="headerlink" href="#list

<div role="contentinfo">
<p>&#169; Copyright Kuźnia Rdzeni, 2023.
<span class="lastupdated">Last updated on 10:40 2023-10-07.
<span class="lastupdated">Last updated on 12:48 2023-10-07.
</span></p>
</div>

Expand Down
98 changes: 49 additions & 49 deletions Current_graph.html
View file

Large diffs are not rendered by default.

2 changes: 1 addition & 1 deletion Development_environment.html
View file
Original file line number Diff line number Diff line change
Expand Up @@ -178,7 +178,7 @@ <h3>build_docs.sh<a class="headerlink" href="#build-docs-sh" title="Permalink to

<div role="contentinfo">
<p>&#169; Copyright Kuźnia Rdzeni, 2023.
<span class="lastupdated">Last updated on 10:40 2023-10-07.
<span class="lastupdated">Last updated on 12:48 2023-10-07.
</span></p>
</div>

Expand Down
2 changes: 1 addition & 1 deletion Home.html
View file
Original file line number Diff line number Diff line change
Expand Up @@ -129,7 +129,7 @@ <h2>Documentation<a class="headerlink" href="#documentation" title="Permalink to

<div role="contentinfo">
<p>&#169; Copyright Kuźnia Rdzeni, 2023.
<span class="lastupdated">Last updated on 10:40 2023-10-07.
<span class="lastupdated">Last updated on 12:48 2023-10-07.
</span></p>
</div>

Expand Down
2 changes: 1 addition & 1 deletion Problem-checklist.html
View file
Original file line number Diff line number Diff line change
Expand Up @@ -105,7 +105,7 @@ <h1>Problem checklist<a class="headerlink" href="#problem-checklist" title="Perm

<div role="contentinfo">
<p>&#169; Copyright Kuźnia Rdzeni, 2023.
<span class="lastupdated">Last updated on 10:40 2023-10-07.
<span class="lastupdated">Last updated on 12:48 2023-10-07.
</span></p>
</div>

Expand Down
2 changes: 1 addition & 1 deletion Transactions.html
View file
Original file line number Diff line number Diff line change
Expand Up @@ -267,7 +267,7 @@ <h3>Transaction and method nesting<a class="headerlink" href="#transaction-and-m

<div role="contentinfo">
<p>&#169; Copyright Kuźnia Rdzeni, 2023.
<span class="lastupdated">Last updated on 10:40 2023-10-07.
<span class="lastupdated">Last updated on 12:48 2023-10-07.
</span></p>
</div>

Expand Down
96 changes: 48 additions & 48 deletions _sources/auto_graph.rst.txt
View file
Original file line number Diff line number Diff line change
Expand Up @@ -6,39 +6,39 @@
subgraph Core["core Core"]
Core_InitFreeRFFifo["InitFreeRFFifo"]
subgraph WishboneMaster["wb_master_instr WishboneMaster"]
WishboneMaster_result["result"]
WishboneMaster_request["request"]
WishboneMaster_result["result"]
end
subgraph WishboneMaster1["wb_master_data WishboneMaster"]
WishboneMaster1_result["result"]
WishboneMaster1_request["request"]
end
subgraph FIFO["fifo_fetch FIFO"]
FIFO_write["write"]
FIFO_read["read"]
FIFO_write["write"]
end
subgraph BasicFifo["free_rf_fifo BasicFifo"]
BasicFifo_read["read"]
BasicFifo_write["write"]
end
subgraph SimpleWBCacheRefiller["icache_refiller SimpleWBCacheRefiller"]
SimpleWBCacheRefiller_SimpleWBCacheRefiller["SimpleWBCacheRefiller"]
SimpleWBCacheRefiller_accept_refill["accept_refill"]
SimpleWBCacheRefiller_start_refill["start_refill"]
SimpleWBCacheRefiller_SimpleWBCacheRefiller["SimpleWBCacheRefiller"]
end
subgraph ICache["icache ICache"]
ICache_accept_res["accept_res"]
ICache_ICache["ICache"]
ICache_accept_res["accept_res"]
ICache_issue_req["issue_req"]
ICache_ICache1["ICache"]
ICache_ICache2["ICache"]
ICache_issue_req["issue_req"]
subgraph FIFO1["req_fifo FIFO"]
FIFO1_write["write"]
FIFO1_read["read"]
FIFO1_write["write"]
end
subgraph Forwarder["res_fwd Forwarder"]
Forwarder_write["write"]
Forwarder_read["read"]
Forwarder_write["write"]
end
end
subgraph Fetch["fetch Fetch"]
Expand All @@ -57,16 +57,16 @@
RRAT_commit["commit"]
end
subgraph RegisterFile["RF RegisterFile"]
RegisterFile_write["write"]
RegisterFile_read2["read2"]
RegisterFile_free["free"]
RegisterFile_read1["read1"]
RegisterFile_free["free"]
RegisterFile_read2["read2"]
RegisterFile_write["write"]
end
subgraph ReorderBuffer["ROB ReorderBuffer"]
ReorderBuffer_mark_done["mark_done"]
ReorderBuffer_get_indices["get_indices"]
ReorderBuffer_peek["peek"]
ReorderBuffer_mark_done["mark_done"]
ReorderBuffer_retire["retire"]
ReorderBuffer_peek["peek"]
ReorderBuffer_put["put"]
end
subgraph ExceptionCauseRegister["exception_cause_register ExceptionCauseRegister"]
Expand Down Expand Up @@ -94,25 +94,25 @@
end
subgraph RSFuncBlock["rs_block_0 RSFuncBlock"]
RSFuncBlock_insert["insert"]
RSFuncBlock_select["select"]
RSFuncBlock_update["update"]
RSFuncBlock_get_result["get_result"]
RSFuncBlock_select["select"]
subgraph RS["rs RS"]
RS_update["update"]
RS_select["select"]
RS_RS["RS"]
RS_insert["insert"]
RS_RS["RS"]
RS_take["take"]
RS_RS1["RS"]
RS_RS2["RS"]
RS_RS3["RS"]
RS_update["update"]
end
subgraph AluFuncUnit["func_unit_0 AluFuncUnit"]
AluFuncUnit_accept["accept"]
AluFuncUnit_issue["issue"]
subgraph FIFO2["fifo FIFO"]
FIFO2_write["write"]
FIFO2_read["read"]
FIFO2_write["write"]
end
end
subgraph WakeupSelect["wakeup_select_0 WakeupSelect"]
Expand All @@ -122,8 +122,8 @@
ShiftFuncUnit_accept["accept"]
ShiftFuncUnit_issue["issue"]
subgraph FIFO3["fifo FIFO"]
FIFO3_write["write"]
FIFO3_read["read"]
FIFO3_write["write"]
end
end
subgraph WakeupSelect1["wakeup_select_1 WakeupSelect"]
Expand All @@ -146,8 +146,8 @@
WakeupSelect2_WakeupSelect["WakeupSelect"]
end
subgraph ExceptionFuncUnit["func_unit_3 ExceptionFuncUnit"]
ExceptionFuncUnit_issue["issue"]
ExceptionFuncUnit_accept["accept"]
ExceptionFuncUnit_issue["issue"]
subgraph FIFO6["fifo FIFO"]
FIFO6_read["read"]
FIFO6_write["write"]
Expand Down Expand Up @@ -179,11 +179,11 @@
end
end
subgraph LSUDummy["rs_block_1 LSUDummy"]
LSUDummy_insert["insert"]
LSUDummy_select["select"]
LSUDummy_update["update"]
LSUDummy_get_result["get_result"]
LSUDummy_insert["insert"]
LSUDummy_precommit["precommit"]
LSUDummy_get_result["get_result"]
subgraph LSUDummyInternals["internal LSUDummyInternals"]
LSUDummyInternals_LSUDummyInternals["LSUDummyInternals"]
LSUDummyInternals_LSUDummyInternals1["LSUDummyInternals"]
Expand All @@ -203,8 +203,8 @@
CSRRegister_write["write"]
end
subgraph CSRRegister1["register_high CSRRegister"]
CSRRegister1_write["write"]
CSRRegister1_read["read"]
CSRRegister1_write["write"]
end
end
subgraph DoubleCounterCSR1["csr_time DoubleCounterCSR"]
Expand All @@ -214,54 +214,54 @@
CSRRegister2_write["write"]
end
subgraph CSRRegister3["register_high CSRRegister"]
CSRRegister3_read["read"]
CSRRegister3_write["write"]
CSRRegister3_read["read"]
end
end
subgraph CSRRegister4["mcause CSRRegister"]
CSRRegister4_write["write"]
end
end
subgraph FIFO7["fifo_decode FIFO"]
FIFO7_read["read"]
FIFO7_write["write"]
FIFO7_read["read"]
end
subgraph Decode["decode Decode"]
Decode_Decode["Decode"]
end
subgraph Scheduler["scheduler Scheduler"]
subgraph FIFO8["alloc_rename_buf FIFO"]
FIFO8_write["write"]
FIFO8_read["read"]
FIFO8_write["write"]
end
subgraph RegAllocation["reg_alloc RegAllocation"]
RegAllocation_RegAllocation["RegAllocation"]
end
subgraph FIFO9["rename_out_buf FIFO"]
FIFO9_write["write"]
FIFO9_read["read"]
FIFO9_write["write"]
end
subgraph Renaming["renaming Renaming"]
Renaming_Renaming["Renaming"]
end
subgraph FIFO10["reg_alloc_out_buf FIFO"]
FIFO10_read["read"]
FIFO10_write["write"]
FIFO10_read["read"]
end
subgraph ROBAllocation["rob_alloc ROBAllocation"]
ROBAllocation_ROBAllocation["ROBAllocation"]
end
subgraph FIFO11["rs_select_out_buf FIFO"]
FIFO11_read["read"]
FIFO11_write["write"]
FIFO11_read["read"]
end
subgraph RSSelection["rs_selector RSSelection"]
RSSelection_RSSelection["RSSelection"]
RSSelection_RSSelection1["RSSelection"]
RSSelection_RSSelection2["RSSelection"]
subgraph Forwarder3["forwarder Forwarder"]
Forwarder3_write["write"]
Forwarder3_read["read"]
Forwarder3_write["write"]
end
end
subgraph RSInsertion["rs_insertion RSInsertion"]
Expand All @@ -281,8 +281,8 @@
CSRRegister5_write["write"]
end
subgraph CSRRegister6["register_high CSRRegister"]
CSRRegister6_read["read"]
CSRRegister6_write["write"]
CSRRegister6_read["read"]
end
end
end
Expand All @@ -300,7 +300,7 @@
end
end
Core_InitFreeRFFifo --> BasicFifo_write
Retirement_Retirement1 --> BasicFifo_write
Retirement_Retirement --> BasicFifo_write
SimpleWBCacheRefiller_SimpleWBCacheRefiller --> WishboneMaster_request
ICache_ICache --> Forwarder_write
ICache_ICache2 --> SimpleWBCacheRefiller_start_refill
Expand Down Expand Up @@ -353,26 +353,26 @@
ResultAnnouncement_ResultAnnouncement --> RSFuncBlock_update
ResultAnnouncement_ResultAnnouncement --> RS_update
ResultAnnouncement_ResultAnnouncement --> LSUDummy_update
RS_RS2 --> WakeupSelect_WakeupSelect
RS_RS1 --> WakeupSelect_WakeupSelect
RS_take --> WakeupSelect_WakeupSelect
RS_take --> WakeupSelect1_WakeupSelect
RS_take --> WakeupSelect2_WakeupSelect
RS_take --> WakeupSelect3_WakeupSelect
WakeupSelect_WakeupSelect --> AluFuncUnit_issue
WakeupSelect_WakeupSelect --> FIFO2_write
RS_RS1 --> WakeupSelect1_WakeupSelect
RS_RS2 --> WakeupSelect1_WakeupSelect
WakeupSelect1_WakeupSelect --> ShiftFuncUnit_issue
WakeupSelect1_WakeupSelect --> FIFO3_write
RS_RS3 --> WakeupSelect2_WakeupSelect
WakeupSelect2_WakeupSelect --> JumpBranchFuncUnit_issue
WakeupSelect2_WakeupSelect --> ExceptionCauseRegister_report
WakeupSelect3_WakeupSelect --> ExceptionCauseRegister_report
LSUDummyInternals_LSUDummyInternals2 --> ExceptionCauseRegister_report
LSUDummyInternals_LSUDummyInternals1 --> ExceptionCauseRegister_report
LSUDummyInternals_LSUDummyInternals --> ExceptionCauseRegister_report
ReorderBuffer_get_indices --> WakeupSelect2_WakeupSelect
ReorderBuffer_get_indices --> WakeupSelect3_WakeupSelect
ReorderBuffer_get_indices --> LSUDummyInternals_LSUDummyInternals2
ReorderBuffer_get_indices --> LSUDummyInternals_LSUDummyInternals1
ReorderBuffer_get_indices --> LSUDummyInternals_LSUDummyInternals
WakeupSelect2_WakeupSelect --> FIFO4_write
WakeupSelect2_WakeupSelect --> FIFO5_write
RS_RS --> WakeupSelect3_WakeupSelect
Expand All @@ -390,26 +390,26 @@
FIFO4_read --> ConnectTrans4_ConnectTrans
ExceptionFuncUnit_accept --> ConnectTrans5_ConnectTrans
FIFO6_read --> ConnectTrans5_ConnectTrans
LSUDummyInternals_LSUDummyInternals --> WishboneMaster1_request
WishboneMaster1_result --> LSUDummyInternals_LSUDummyInternals1
LSUDummyInternals_LSUDummyInternals2 --> WishboneMaster1_request
WishboneMaster1_result --> LSUDummyInternals_LSUDummyInternals
ConnectTrans_ConnectTrans --> Forwarder1_write
ConnectTrans1_ConnectTrans --> Forwarder1_write
RSFuncBlock_get_result --> ConnectTrans_ConnectTrans
Collector1_method --> ConnectTrans_ConnectTrans
Forwarder2_read --> ConnectTrans_ConnectTrans
LSUDummy_get_result --> ConnectTrans1_ConnectTrans
ReorderBuffer_peek --> Retirement_Retirement
Retirement_Retirement --> LSUDummy_precommit
ReorderBuffer_retire --> Retirement_Retirement1
ExceptionCauseRegister_get --> Retirement_Retirement1
Retirement_Retirement1 --> CSRRegister4_write
Retirement_Retirement1 --> RRAT_commit
Retirement_Retirement1 --> RegisterFile_free
Retirement_Retirement1 <--> DoubleCounterCSR2_increment
CSRRegister5_read --> Retirement_Retirement1
Retirement_Retirement1 --> CSRRegister5_write
CSRRegister6_read --> Retirement_Retirement1
Retirement_Retirement1 --> CSRRegister6_write
ReorderBuffer_peek --> Retirement_Retirement1
Retirement_Retirement1 --> LSUDummy_precommit
ReorderBuffer_retire --> Retirement_Retirement
ExceptionCauseRegister_get --> Retirement_Retirement
Retirement_Retirement --> CSRRegister4_write
Retirement_Retirement --> RRAT_commit
Retirement_Retirement --> RegisterFile_free
Retirement_Retirement <--> DoubleCounterCSR2_increment
CSRRegister5_read --> Retirement_Retirement
Retirement_Retirement --> CSRRegister5_write
CSRRegister6_read --> Retirement_Retirement
Retirement_Retirement --> CSRRegister6_write
GenericCSRRegisters_GenericCSRRegisters <--> DoubleCounterCSR_increment
CSRRegister_read --> GenericCSRRegisters_GenericCSRRegisters
GenericCSRRegisters_GenericCSRRegisters --> CSRRegister_write
Expand Down
Loading

0 comments on commit cd0a0c0

Please sign in to comment.