Synthesize different core versions #407
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Action run is here: https://github.com/kuznia-rdzeni/coreblocks/actions/runs/5424401768 There is surprisingly little difference between |
lekcyjna123
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Jun 30, 2023
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By the way: current configurations look weird. In particular, the ROB is quite large (128 entries) compared to RS sizes (4 and 2 entries). |
piotro888
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Jun 30, 2023
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Approved.
I also think that core configurations need rethinking (and optimization). Adding additional core configuration between basic and full would be helpful.
- Tiny core config could probably use RV32E and smaller struct sizes when implemented
- Basic config is good as is - standard, usable rv32i good for baseline benchmarks and simple use cases (probably without priv mode - requires zicsr, but thats discussable)
- Some new config that supplies priv mode and some common set of useful extenstions, to be nice for generic usage
- And current Full config that is helpful for arch tests and testing possibilities
- We could also add some configurations accoring to RISCV Profiles that was stated in some issue.
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Synthesis and verilog generation are currently kinda copy-pastey, and that's fine for now - cleaning this up (maybe unifying the two?) can be done later.
Fixes #402.