diff --git a/litex_boards/targets/kc705.py b/litex_boards/targets/kc705.py index 482725084..a47915279 100755 --- a/litex_boards/targets/kc705.py +++ b/litex_boards/targets/kc705.py @@ -86,7 +86,7 @@ def __init__(self, sys_clk_freq=int(150e6), with_ethernet=False, with_sata=False self.add_csr("ethphy") self.add_ethernet(phy=self.ethphy) - # SATA (Experimental) ---------------------------------------------------------------------- + # SATA ------------------------------------------------------------------------------------- if with_sata: from litex.build.generic_platform import Subsignal, Pins from litesata.phy import LiteSATAPHY diff --git a/litex_boards/targets/nexys_video.py b/litex_boards/targets/nexys_video.py index c16d8d27d..96c35c3c0 100755 --- a/litex_boards/targets/nexys_video.py +++ b/litex_boards/targets/nexys_video.py @@ -50,7 +50,7 @@ def __init__(self, platform, sys_clk_freq): # BaseSoC ------------------------------------------------------------------------------------------ class BaseSoC(SoCCore): - def __init__(self, sys_clk_freq=int(100e6), with_ethernet=False, **kwargs): + def __init__(self, sys_clk_freq=int(100e6), with_ethernet=False, with_sata=False, **kwargs): platform = nexys_video.Platform() # SoCCore ---------------------------------------------------------------------------------- @@ -87,6 +87,36 @@ def __init__(self, sys_clk_freq=int(100e6), with_ethernet=False, **kwargs): self.add_csr("ethphy") self.add_ethernet(phy=self.ethphy) + # SATA ------------------------------------------------------------------------------------- + if with_sata: + from litex.build.generic_platform import Subsignal, Pins + from litesata.phy import LiteSATAPHY + + # IOs + _sata_io = [ + # AB09-FMCRAID / https://www.dgway.com/AB09-FMCRAID_E.html + ("fmc2sata", 0, + Subsignal("clk_p", Pins("LPC:GBTCLK0_M2C_P")), + Subsignal("clk_n", Pins("LPC:GBTCLK0_M2C_N")), + Subsignal("tx_p", Pins("LPC:DP0_C2M_P")), + Subsignal("tx_n", Pins("LPC:DP0_C2M_N")), + Subsignal("rx_p", Pins("LPC:DP0_M2C_P")), + Subsignal("rx_n", Pins("LPC:DP0_M2C_N")) + ), + ] + platform.add_extension(_sata_io) + + # PHY + self.submodules.sata_phy = LiteSATAPHY(platform.device, + pads = platform.request("fmc2sata"), + gen = "gen2", + clk_freq = sys_clk_freq, + data_width = 16) + self.add_csr("sata_phy") + + # Core + self.add_sata(phy=self.sata_phy, mode="read+write") + # Leds ------------------------------------------------------------------------------------- self.submodules.leds = LedChaser( pads = platform.request_all("user_led"), @@ -101,12 +131,13 @@ def main(): parser.add_argument("--load", action="store_true", help="Load bitstream") builder_args(parser) soc_sdram_args(parser) - parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support") + parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support") parser.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support") - parser.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support") + parser.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support") + parser.add_argument("--with-sata", action="store_true", help="Enable SATA support (over FMCRAID)") args = parser.parse_args() - soc = BaseSoC(with_ethernet=args.with_ethernet, **soc_sdram_argdict(args)) + soc = BaseSoC(with_ethernet=args.with_ethernet, with_sata=args.with_sata, **soc_sdram_argdict(args)) assert not (args.with_spi_sdcard and args.with_sdcard) if args.with_spi_sdcard: soc.add_spi_sdcard()