platforms: cleanup pass to uniformize comments/separators/orders.

litex-hub · Nov 3, 2020 · c093d0d · c093d0d
1 parent 8d26c24
commit c093d0d
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Showing 57 changed files with 894 additions and 681 deletions.
diff --git a/litex_boards/platforms/ac701.py b/litex_boards/platforms/ac701.py
@@ -11,23 +11,24 @@
 # IOs ----------------------------------------------------------------------------------------------
 
 _io = [
-    ("user_led", 0, Pins("M26"), IOStandard("LVCMOS33")),
-    ("user_led", 1, Pins("T24"), IOStandard("LVCMOS33")),
-    ("user_led", 2, Pins("T25"), IOStandard("LVCMOS33")),
-    ("user_led", 3, Pins("R26"), IOStandard("LVCMOS33")),
-
-    ("cpu_reset", 0, Pins("U4"), IOStandard("SSTL15")),
-
+    # Clk / Rst
     ("clk200", 0,
         Subsignal("p", Pins("R3"), IOStandard("DIFF_SSTL15")),
         Subsignal("n", Pins("P3"), IOStandard("DIFF_SSTL15"))
     ),
-
     ("clk156", 0,
         Subsignal("p", Pins("M21"), IOStandard("LVDS_25")),
         Subsignal("n", Pins("M22"), IOStandard("LVDS_25"))
     ),
+    ("cpu_reset", 0, Pins("U4"), IOStandard("SSTL15")),
+
+    # Leds
+    ("user_led", 0, Pins("M26"), IOStandard("LVCMOS33")),
+    ("user_led", 1, Pins("T24"), IOStandard("LVCMOS33")),
+    ("user_led", 2, Pins("T25"), IOStandard("LVCMOS33")),
+    ("user_led", 3, Pins("R26"), IOStandard("LVCMOS33")),
 
+    # Serial
     ("serial", 0,
         Subsignal("cts", Pins("V19")),
         Subsignal("rts", Pins("W19")),
@@ -36,12 +37,12 @@
         IOStandard("LVCMOS18")
     ),
 
+    # RGMII Ethernet
     ("eth_clocks", 0,
         Subsignal("tx", Pins("U22")),
         Subsignal("rx", Pins("U21")),
         IOStandard("LVCMOS18")
     ),
-
     ("eth", 0,
         Subsignal("rx_ctl",  Pins("U14")),
         Subsignal("rx_data", Pins("U17 V17 V16 V14")),
@@ -55,6 +56,7 @@
         IOStandard("LVCMOS18"),
     ),
 
+    # DDR3 SDRAM
     ("ddram", 0,
         Subsignal("a", Pins(
             "M4 J3 J1 L4 K5 M7 K1 M6",
@@ -90,6 +92,7 @@
         Misc("SLEW=FAST"),
     ),
 
+    # PCIe
     ("pcie_x1", 0,
         Subsignal("rst_n", Pins("M20"), IOStandard("LVCMOS25")),
         Subsignal("clk_p", Pins("F11")),
@@ -100,13 +103,13 @@
         Subsignal("tx_n",  Pins("C10"))
     ),
 
-    ("vadj_on_b", 0, Pins("R16"), IOStandard("LVCMOS25")),
-
+    # GTP RefClk
     ("gtp_refclk", 0,
      Subsignal("p", Pins("AA13")),
      Subsignal("n", Pins("AB13"))
     ),
 
+    # SFP
     ("sfp", 0,
         Subsignal("txp", Pins("AC10")),
         Subsignal("txn", Pins("AD10")),
@@ -117,6 +120,10 @@
     ("sfp_mgt_clk_sel1", 0, Pins("C24"), IOStandard("LVCMOS25")),
     ("sfp_tx_disable_n", 0, Pins("R18"), IOStandard("LVCMOS33")),
     ("sfp_rx_los",       0, Pins("R23"), IOStandard("LVCMOS33")),
+
+    # Others
+    ("vadj_on_b", 0, Pins("R16"), IOStandard("LVCMOS25")),
+
 ]
 
 # Connectors ---------------------------------------------------------------------------------------

diff --git a/litex_boards/platforms/acorn_cle_215.py b/litex_boards/platforms/acorn_cle_215.py
@@ -14,19 +14,19 @@
 # IOs ----------------------------------------------------------------------------------------------
 
 _io = [
-    # clk / rst
+    # Clk / Rst
     ("clk200", 0,
         Subsignal("p", Pins("J19"), IOStandard("DIFF_SSTL15")),
         Subsignal("n", Pins("H19"), IOStandard("DIFF_SSTL15"))
     ),
 
-    # leds
+    # Leds
     ("user_led", 0, Pins("G3"), IOStandard("LVCMOS33")),
     ("user_led", 1, Pins("H3"), IOStandard("LVCMOS33")),
     ("user_led", 2, Pins("G4"), IOStandard("LVCMOS33")),
     ("user_led", 3, Pins("H4"), IOStandard("LVCMOS33")),
 
-    # spiflash
+    # SPIFlash
     ("spiflash", 0,
         Subsignal("cs_n", Pins("T19")),
         Subsignal("mosi", Pins("P22")),
@@ -36,7 +36,7 @@
         IOStandard("LVCMOS33")
     ),
 
-    # pcie
+    # PCIe
     ("pcie_clkreq_n", 0, Pins("G1"), IOStandard("LVCMOS33")),
     ("pcie_x4", 0,
         Subsignal("rst_n", Pins("J1"), IOStandard("LVCMOS33"), Misc("PULLUP=TRUE")),
@@ -48,7 +48,7 @@
         Subsignal("tx_n",  Pins("A6 A4 C5 C7")),
     ),
 
-    # dram
+    # DDR3 SDRAM
     ("ddram", 0,
         Subsignal("a", Pins(
             "M15 L21 M16 L18 K21 M18 M21 N20",

diff --git a/litex_boards/platforms/aller.py b/litex_boards/platforms/aller.py
@@ -12,23 +12,23 @@
 # IOs ----------------------------------------------------------------------------------------------
 
 _io = [
-    # clk / rst
+    # Clk / Rst
     ("clk100", 0, Pins("W19"), IOStandard("LVCMOS33")),
 
-    # leds (only a single rgb led, aliased here also)
+    # Leds (only a single rgb led, aliased here also)
     ("user_led", 0, Pins("AB21"), IOStandard("LVCMOS33")),
     ("user_led", 1, Pins("AB22"), IOStandard("LVCMOS33")),
     ("user_led", 2, Pins("U20"),  IOStandard("LVCMOS33")),
 
-    # rgb led, active-low
+    # RGB led, active-low
     ("rgb_led", 0,
         Subsignal("r", Pins("AB21")),
         Subsignal("g", Pins("AB22")),
         Subsignal("b", Pins("U20")),
         IOStandard("LVCMOS33"),
     ),
 
-    # flash
+    # SPIFlash
     ("flash", 0,
         Subsignal("cs_n",  Pins("T19")),
         Subsignal("mosi",  Pins("P22")),
@@ -37,14 +37,13 @@
         Subsignal("rst_n", Pins("R19")),
         IOStandard("LVCMOS33")
     ),
-
     ("flash4x", 0,  # clock needs to be accessed through STARTUPE2
         Subsignal("cs_n", Pins("T19")),
         Subsignal("dq",   Pins("P22", "R22", "P21", "R21")),
         IOStandard("LVCMOS33")
     ),
 
-    # tpm
+    # TPM
     ("tpm", 0,
         Subsignal("clk",   Pins("W20")),
         Subsignal("rst_n", Pins("V19")),
@@ -54,7 +53,7 @@
         IOStandard("LVCMOS33"),
     ),
 
-    # pcie
+    # PCIe
     ("pcie_x1", 0,
         Subsignal("rst_n", Pins("AB20"), IOStandard("LVCMOS33"), Misc("PULLUP=TRUE")),
         Subsignal("clk_p", Pins("F6")),
@@ -75,7 +74,7 @@
         Subsignal("tx_n",  Pins("A4 C5 A6 C7"))
     ),
 
-    # dram
+    # DDR3 SDRAM
     ("ddram", 0,
         Subsignal("a", Pins(
             "U6 T5 Y6 T6  V2 T4 Y2 R2",

diff --git a/litex_boards/platforms/alveo_u250.py b/litex_boards/platforms/alveo_u250.py
@@ -14,7 +14,7 @@
 # IOs (initially auto-generated by extract_xdc_pins.py) ---------------------------------------------
 
 _io = [
-    # clk / rst
+    # Clk / Rst
     ("clk300", 0,
         Subsignal("n", Pins("AY38"), IOStandard("DIFF_SSTL12")),
         Subsignal("p", Pins("AY37"), IOStandard("DIFF_SSTL12")),
@@ -33,24 +33,25 @@
     ),
     ("cpu_reset", 0, Pins("AL20"), IOStandard("LVCMOS12")),
 
-    # led
+    # Leds
     ("user_led", 0, Pins("BC21"), IOStandard("LVCMOS12")),
     ("user_led", 1, Pins("BB21"), IOStandard("LVCMOS12")),
     ("user_led", 2, Pins("BA20"), IOStandard("LVCMOS12")),
 
-    # switches
+    # Switches
     ("set_sw",  0, Pins("AL21")),
     ("user_sw", 0, Pins("AN22"), IOStandard("LVCMOS12")),
     ("user_sw", 1, Pins("AM19"), IOStandard("LVCMOS12")),
     ("user_sw", 2, Pins("AL19"), IOStandard("LVCMOS12")),
     ("user_sw", 3, Pins("AP20"), IOStandard("LVCMOS12")),
 
-    # gpio
+    # GPIOs
     ("gpio_msp", 0, Pins("AR20"), IOStandard("LVCMOS12")),
     ("gpio_msp", 1, Pins("AM20"), IOStandard("LVCMOS12")),
     ("gpio_msp", 2, Pins("AM21"), IOStandard("LVCMOS12")),
     ("gpio_msp", 3, Pins("AN21"), IOStandard("LVCMOS12")),
 
+    # Serial
     ("serial", 0,
         Subsignal("rx", Pins("BF18"), IOStandard("LVCMOS12")),
         Subsignal("tx", Pins("BB20"), IOStandard("LVCMOS12")),
@@ -60,7 +61,7 @@
         Subsignal("tx", Pins("BB19"), IOStandard("LVCMOS12")),
     ),
 
-    # ddram
+    # DDR4 SDRAM
     ("ddram_reset_gate", 0, Pins("AU21"), IOStandard("LVCMOS12")),
     ("ddram", 0,
         Subsignal("a", Pins(
@@ -235,14 +236,14 @@
         Misc("SLEW=FAST")
     ),
 
-    # i2c
+    # I2C
     ("i2c_rst_n", 0, Pins("BF19"), IOStandard("LVCMOS12")),
     ("i2c", 0,
         Subsignal("scl", Pins("BF20"), IOStandard("LVCMOS12")),
         Subsignal("sda", Pins("BF17"), IOStandard("LVCMOS12")),
     ),
 
-    # si570
+    # SI570 Clock
     ("user_si570_clock", 0,
         Subsignal("n", Pins("AV19"), IOStandard("DIFF_SSTL12")),
         Subsignal("p", Pins("AU19"), IOStandard("DIFF_SSTL12")),
@@ -256,7 +257,7 @@
         Subsignal("p", Pins("T11")),
     ),
 
-    # pcie
+    # PCIe
     ("pcie_x16", 0,
         Subsignal("rst_n", Pins("BD21"), IOStandard("LVCMOS12")),
         Subsignal("clk_n", Pins("AM10")),
@@ -275,7 +276,7 @@
             "AP7 AR9 AT7 AU9 AV7 BB5 BD5 BF5")),
     ),
 
-    # pcie
+    # PCIe
     ("pcie_x4", 0,
         Subsignal("rst_n", Pins("BD21"), IOStandard("LVCMOS12")),
         Subsignal("clk_n", Pins("AM10")),
@@ -286,7 +287,7 @@
         Subsignal("tx_p",  Pins("AF7 AG9 AH7 AJ9")),
     ),
 
-    # qsfp28
+    # QSFP28
     ("qsfp28", 0,
         Subsignal("clk_n", Pins("K10")),
         Subsignal("clk_p", Pins("K11")),
@@ -321,6 +322,8 @@
     ),
 ]
 
+# Connectors ---------------------------------------------------------------------------------------
+
 _connectors = []
 
 # Platform -----------------------------------------------------------------------------------------