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SystemVerilog Language Support #2048

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sw23 opened this issue Jul 20, 2020 · 0 comments
Closed

SystemVerilog Language Support #2048

sw23 opened this issue Jul 20, 2020 · 0 comments
Milestone
August 2020

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@sw23
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sw23 commented Jul 20, 2020

This work item is to add SystemVerilog language support to enable Verilog and SystemVerilog file syntax highlighting.

We have put together a small team to work on this as part of a Hackathon project next week. We hope to have a PR for this in place late next week!

We haven't seen any existing work to support this language but think we have everything we need from the docs. Any comments, tips, or feedback are welcome!
@xadegunt xadegunt mentioned this issue Jul 30, 2020
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@alexdima alexdima added this to the August 2020 milestone Sep 9, 2020
@alexdima alexdima closed this as completed Sep 9, 2020
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@alexdima @sw23